M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 371
M30853FJGP#U3
Manufacturer Part Number
M30853FJGP#U3
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FJGP#U3M30853FJGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M
R
R
e
E
3
. v
J
2
Figure 23.22 C0GMR0, C0LMAR0 and C0LMBR0 Registers
0
C
23.1.19 CANi Global Mask Register, CANi Local Mask Register A and CANi Local Mask
1
9
0 .
8 /
B
0
3
5
0
3
G
J
7
u
o r
CANi Global Mask Register Standard ID0
CANi Local Mask Register A Standard ID0
CANi Local Mask Register B Standard ID0
0 -
. l
b7
u
NOTES:
0
1
p
, 1
0
b6
Register B (CiGMRk, CiLMARk and CiLMBRk Registers)
3
1. The CiGMR0, CiLMAR0 and CiLMBR0 registers can be accessed only when the BANKSEL bit in
2. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after
3. The C0LMAR0 register shares the same address with the C0MCTL0 register.
4. The C1LMAR0 register shares the same address with the C1MCTL0 register.
5. The C0LMBR0 register shares the same address with the C0MCTL8 register.
6. The C1LMBR0 register shares the same address with the C1MCTL8 register.
(
2
M
b5
C1GMR0, C1LMAR0 and C1LMBR0 Registers
0
the CiCTLR1 register is set to "1" (mask register selected).
reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "1".
3
0
2
5
b4
C
8 /
b3
Page 346
, 5
b2
M
b1
3
2
C
b0
f o
8 /
(b7 - b5)
4
5
SID10M
Symbol
SID6M
SID7M
SID8M
SID9M
9
) T
Bit
4
Symbol
C0GMR0, C1GMR0
C0LMAR0, C1LMAR0
C0LMBR0, C1LMBR0
Standard ID6
Standard ID7
Standard ID8
Standard ID9
Standard ID10
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Bit Name
Address
0228
0230
0238
16
16 (3)
16
(1)
, 02A8
(5)
(1)
(1)
0: No ID is verified
1: ID is verified
, 02B0
, 02B8
(i=0, 1)
16
16 (4)
16
(6)
Function
After Reset
XXX0 0000
XXX0 0000
XXX0 0000
(i=0,1, k=0 to 4)
(2)
2
2
2
23. CAN Module
RW
RW
RW
RW
RW
RW
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