M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 369
![IC M32C MCU FLASH 100LQFP](/photos/12/22/122251/m30853fjgp_u3_sml.jpg)
M30853FJGP#U3
Manufacturer Part Number
M30853FJGP#U3
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FJGP#U3M30853FJGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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2
Figure 23.20 C0SSCTLR and C1SSCTLR Registers
0
C
23.1.17 CANi Single-Shot Control Register (CiSSCTLR Register)
1
9
0 .
8 /
B
According to the CAN Specification 2.0 Part B, if the arbitration lost or transmission error causes a
transmit failure, the microcomputer continues transmitting data until the transmission is completed. The
CiSSCTLR register determines whether or not, and from which slot, data is re-transmitted.
In single-shot mode, if the arbitration lost or transmission error causes a transmission failure, data is not
transmitted again. When the SSCj bit (j=0 to 15) is set to "1", the corresponding message slot j is in
single-shot mode.
0
3
5
0
3
G
J
7
u
o r
0 -
. l
b15
u
0
1
CANi Single-Shot Control Register
p
, 1
0
NOTES:
3
(
2
M
1. Set the CiSSCTLR register after the CiMCTLj register (j=0 to 15) in a slot, corresponding to the bit to
2.The CiSSCTLR register can be accessed only when the BANKSEL bit in the CiCTLR1 register is set to
3. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after
0
3
0
be changed, is set to "00
"0" (message slot control register and single-shot register selected).
reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "0".
2
5
C
b8
8 /
Page 344
, 5
b7
M
3
2
C
f o
8 /
b0
4
5
9
) T
4
Symbol
SSC15
SSC14
SSC13
SSC12
SSC10
SSC11
SSC9
SSC8
SSC7
SSC6
SSC5
SSC4
SSC3
SSC2
SSC1
SSC0
16
Bit
Symbol
C0SSCTLR
C1SSCTLR
".
Message Slot 15 Single-Shot
Control Bit
Message Slot 14 Single-Shot
Control Bit
Message Slot 13 Single-Shot
Control Bit
Message Slot 12 Single-Shot
Control Bit
Message Slot 11 Single-Shot
Control Bit
Message Slot 10 Single-Shot
Control Bit
Message Slot 9 Single-Shot
Control Bit
Message Slot 8 Single-Shot
Control Bit
Message Slot 7 Single-Shot
Control Bit
Message Slot 6 Single-Shot
Control Bit
Message Slot 5 Single-Shot
Control Bit
Message Slot 4 Single-Shot
Control Bit
Message Slot 3 Single-Shot
Control Bit
Message Slot 2 Single-Shot
Control Bit
Message Slot 1 Single-Shot
Control Bit
Message Slot 0 Single-Shot
Control Bit
Bit Name
Address
0221
02A1
(i=0, 1)
16
16
- 0220
- 02A0
(1, 2)
16
16
0: Single-shot mode not used
1: Use single-shot mode
After Reset
0000
0000
Function
16
16
(3)
(i=0, 1)
23. CAN Module
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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