M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 366

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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2
Figure 23.17 C0EFR and C1EFR Registers
0
C
23.1.15 CANi Error Factor Register (CiEFR Register)
1
9
8 /
0 .
B
The CiEFR register indicates the cause of error when a communication error is detected. Set the follow-
ing bits to "0" by program because they are not changed "1" to "0" automatically.
Use the MOV instruction, instead of the bit clear instruction, to set each bit in the CiEFR register to "0".
0
3
5
23.1.15.1 ACKE Bit
23.1.15.2 CRCE Bit
23.1.15.3 FORME Bit
23.1.15.4 STFE Bit
23.1.15.5 BITE0 Bit
23.1.15.6 BITE1 Bit
23.1.15.7 RCVE Bit
23.1.15.8 TRE Bit
The ACKE bit is set to "1" when an ACK error is detected.
The CRC bit is set to "1" when a CRC error is detected.
The FORME bit is set to "1" when a form error is detected.
The STFE bit is set to "1" when a stuff error is detected.
The BITE0 bit is set to "1" when a bit error is detected while transmitting recessive "H".
The BITE1 bit is set to "1" when a bit error is detected while transmitting dominant "L".
The RCVE bit is set to "1" when an error is detected while receiving data.
The TRE bit is set to "1" when an error is detected while transmitting data.
0
G
3
J
7
u
o r
Bits not being changed to "0" must be set to "1".
0 -
. l
For example: To set the ACKE bit for CAN0 to "0"
u
CANi Error Factor Register
0
1
b7
p
, 1
0
NOTES:
3
(
b6
2
M
1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after
2. Set to "0" by program. If it is set to "1", the value before setting to "1" remains.
0
3
Assembly language:
C language:
0
b5
reset and supplying the clock to the CAN module.
2
5
C
b4
8 /
Page 341
b3
, 5
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b2
3
b1
2
C
f o
b0
8 /
4
5
9
) T
FORME
Symbol
CRCE
ACKE
BITE0
BITE1
4
STFE
RCVE
TRE
Bit
Symbol
C0EFR
C1EFR
ACK Error Detect Bit
CRC Error Detect Bit
FORM Error Detect Bit
Stuff Error Detect Bit
Bit Error Detect Bit 0
Bit Error Detect Bit 1
Transmit Error Detect Bit
mov.b#0FEh, C0EFR
c0efr = 0xFE;
Receive Error Detect Bit
(i=0, 1)
Bit Name
Address
0216
0296
16
16
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
0: Detects no ACK error
1: Detects an ACK error
0: Detects no CRC error
1: Detects a CRC error
0: Detects no form error
1: Detects a form error
0: Detects no stuff error
1: Detects a stuff error
0: Detects no bit error while transmitting "H"
1: Detects a bit error while transmitting "H"
0: Detects no bit error while transmitting "L"
1: Detects a bit error while transmitting "L"
0: Detects no error while receiving data
1: Detects an error while receiving data
0: Detects no error while transmitting data
1: Detects an error while transmitting data
(i=0, 1)
After Reset
00
00
Function
16
16
(1)
23. CAN Module
RW
RW
RW
RW
RW
RW
RW
RW
RW