PIC18F4331-I/P Microchip Technology, PIC18F4331-I/P Datasheet - Page 364

• Manufacturer Part Number: PIC18F4331-I/P
• Description: IC PIC MCU FLASH 4KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4331-I/P

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4431 - BOARD DAUGHTER ICEPIC3DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Details

PIC18F2331/2431/4331/4431
FIGURE 25-13:
TABLE 25-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE, CKE = 0)
DS39616C-page 362
70
71
71A
72
72A
73
73A
74
75
76
77
78
79
80
83
Note 1:
Param
No.
(CKP = 0)
(CKP = 1)
SDI
SDI
SCK
SDO
Note:
SS
SCK
2:
TssL2scH,
TssL2scL
TscH
TscL
TdiV2scH,
TdiV2scL
T
TscH2diL,
TscL2diL
TdoR
TdoF
TssH2doZ SS ↑ to SDO Output High-Impedance
TscR
TscF
TscH2doV,
TscL2doV
TscH2ssH,
TscL2ssH
Symbol
B
Requires the use of Parameter 73A.
Only if Parameter 71A and 72A are used.
2
B
Refer to Figure 25-4 for load conditions.
SS ↓ to SCK ↓ or SCK ↑ Input
SCK Input High Time
(Slave mode)
SCK Input Low Time
(Slave mode)
Setup Time of SDI Data Input to SCK Edge
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 T
Hold Time of SDI Data Input to SCK Edge
SDO Data Output Rise Time
SDO Data Output Fall Time
SCK Output Rise Time (Master mode)
SCK Output Fall Time (Master mode)
SDO Data Output Valid after SCK Edge PIC18FXX31
SS ↑ after SCK Edge
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
70
80
71
73
MSb In
MSb
Characteristic
74
72
75, 76
Preliminary
bit 6 - - - - - -1
bit 6 - - - -1
Continuous
Single byte
Continuous
Single byte
PIC18FXX31
PIC18LFXX31
PIC18FXX31
PIC18LFXX31
PIC18LFXX31
78
79
1.25 T
1.25 T
1.5 T
LSb
79
78
LSb In
Min
T
100
100
CY
CY
40
40
—
10
—
—
—
—
CY
CY
CY
83
+ 40
+ 40
+ 30
+ 30
© 2007 Microchip Technology Inc.
77
Max Units Conditions
100
—
—
—
—
—
—
—
25
45
25
50
25
45
25
50
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 2)