PIC18LF2523-I/SP Microchip Technology, PIC18LF2523-I/SP Datasheet - Page 355
![IC PIC MCU FLASH 16KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF2523-I/SP
Manufacturer Part Number
PIC18LF2523-I/SP
Description
IC PIC MCU FLASH 16KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2423-ISP.pdf
(54 pages)
3.PIC18F2423-ISP.pdf
(8 pages)
4.PIC18F2423-ISP.pdf
(34 pages)
5.PIC18F2523-ISO.pdf
(392 pages)
Specifications of PIC18LF2523-I/SP
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
25
Interface Type
I2C/SPI/USART
On-chip Adc
10-chx12-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC18F2221-ISO PDF datasheet
- PIC18F2423-ISP PDF datasheet #2
- PIC18F2423-ISP PDF datasheet #3
- PIC18F2423-ISP PDF datasheet #4
- PIC18F2523-ISO PDF datasheet #5
- Current page: 355 of 392
- Download datasheet (7Mb)
FIGURE 26-14:
TABLE 26-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
© 2007 Microchip Technology Inc.
70
71
71A
72
72A
73
73A
74
75
76
77
78
79
80
83
Note 1:
Param
No.
(CKP = 0)
(CKP = 1)
SDI
SDI
SS
SCK
SCK
SDO
Note:
2:
TssL2scH,
TssL2scL
TscH
TscL
TdiV2scH,
TdiV2scL
Tb2b
TscH2diL,
TscL2diL
TdoR
TdoF
TssH2doZ SS↑ to SDO Output High-Impedance
TscR
TscF
TscH2doV,
TscL2doV
TscH2ssH,
TscL2ssH
Symbol
Requires the use of Parameter #73A.
Only if Parameter #71A and #72A are used.
Refer to Figure 26-4 for load conditions.
SS ↓ to SCK ↓ or SCK ↑ Input
SCK Input High Time
(Slave mode)
SCK Input Low Time
(Slave mode)
Setup Time of SDI Data Input to SCK Edge
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 T
Hold Time of SDI Data Input to SCK Edge
SDO Data Output Rise Time
SDO Data Output Fall Time
SCK Output Rise Time (Master mode) PIC18FXXXX
SCK Output Fall Time (Master mode)
SDO Data Output Valid after SCK Edge PIC18FXXXX
SS ↑ after SCK edge
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
70
80
71
73
MSb In
MSb
Characteristic
74
72
PIC18F2423/2523/4423/4523
75, 76
Preliminary
bit 6 - - - - - -1
bit 6 - - - -1
Continuous
Single Byte
Continuous
Single Byte
PIC18FXXXX
PIC18LFXXXX
PIC18LFXXXX
PIC18LFXXXX
78
79
1.25 T
1.25 T
1.5 T
79
78
LSb In
LSb
Min
100
100
T
40
40
CY
10
CY
—
—
—
—
—
—
—
—
CY
CY
CY
83
+ 40
+ 40
+ 30
+ 30
77
Max Units Conditions
100
25
45
25
50
25
45
25
50
—
—
—
—
—
—
—
—
—
DS39755B-page 353
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 2)
V
V
V
DD
DD
DD
= 2.0V
= 2.0V
= 2.0V
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