PIC18LF2523-I/SP Microchip Technology, PIC18LF2523-I/SP Datasheet - Page 70
![IC PIC MCU FLASH 16KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18LF2523-I/SP
Manufacturer Part Number
PIC18LF2523-I/SP
Description
IC PIC MCU FLASH 16KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2423-ISP.pdf
(54 pages)
3.PIC18F2423-ISP.pdf
(8 pages)
4.PIC18F2423-ISP.pdf
(34 pages)
5.PIC18F2523-ISO.pdf
(392 pages)
Specifications of PIC18LF2523-I/SP
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
1.5KB
Cpu Speed
40MHz
No. Of Timers
4
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
25
Interface Type
I2C/SPI/USART
On-chip Adc
10-chx12-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC18F2221-ISO PDF datasheet
- PIC18F2423-ISP PDF datasheet #2
- PIC18F2423-ISP PDF datasheet #3
- PIC18F2423-ISP PDF datasheet #4
- PIC18F2523-ISO PDF datasheet #5
- Current page: 70 of 392
- Download datasheet (7Mb)
argument at all; they either perform an operation that glo-
PIC18F2423/2523/4423/4523
5.4
While the program memory can be addressed in only
one way – through the program counter – information
in the data memory space can be addressed in several
ways. For most instructions, the addressing mode is
fixed. Other instructions may use up to three modes,
depending on which operands are used and whether or
not the extended instruction set is enabled.
The addressing modes are:
• Inherent
• Literal
• Direct
• Indirect
An additional addressing mode, Indexed Literal Offset,
is available when the extended instruction set is
enabled (XINST Configuration bit = 1). Its operation is
discussed in greater detail in Section 5.5.1 “Indexed
Addressing with Literal Offset”.
5.4.1
Many PIC18 control instructions do not need any
bally affects the device or they operate implicitly on one
register. This addressing mode is known as Inherent
Addressing. Examples include SLEEP, RESET and DAW.
Other instructions work in a similar way but require an
additional explicit argument in the opcode. This is
known as Literal Addressing mode because they
require some literal value as an argument. Examples
include ADDLW and MOVLW, which respectively, add or
move a literal value to the W register. Other examples
include CALL and GOTO, which include a 20-bit
program memory address.
5.4.2
Direct Addressing mode specifies all or part of the
source and/or destination address of the operation
within the opcode itself. The options are specified by
the arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and byte-
oriented instructions use some version of Direct
Addressing by default. All of these instructions include
some 8-bit literal address as their Least Significant
Byte. This address specifies either a register address in
one of the banks of data RAM (Section 5.3.3 “General
Purpose Register File”) or a location in the Access
Bank (Section 5.3.2 “Access Bank”) as the data
source for the instruction.
DS39755B-page 68
Note:
Data Addressing Modes
The execution of some instructions in the
core PIC18 instruction set are changed
when the PIC18 extended instruction set is
enabled. See Section 5.5 “Data Memory
and the Extended Instruction Set” for
more information.
INHERENT AND LITERAL
ADDRESSING
DIRECT ADDRESSING
Preliminary
The Access RAM bit ‘a’ determines how the address is
interpreted. When ‘a’ is ‘1’, the contents of the BSR
(Section 5.3.1 “Bank Select Register (BSR)”) are
used with the address to determine the complete 12-bit
address of the register. When ‘a’ is ‘0’, the address is
interpreted as being a register in the Access Bank.
Addressing that uses the Access RAM is sometimes
also known as Direct Forced Addressing mode.
A few instructions, such as MOVFF, include the entire
12-bit address (either source or destination) in their
opcodes. In these cases, the BSR is ignored entirely.
The destination of the operation’s results is determined
by the destination bit ‘d’. When ‘d’ is ‘1’, the results are
stored back in the source register, overwriting its origi-
nal contents. When ‘d’ is ‘0’, the results are stored in
the W register. Instructions without the ‘d’ argument
have a destination that is implicit in the instruction; their
destination is either the target register being operated
on or the W register.
5.4.3
Indirect Addressing mode allows the user to access a
location in data memory without giving a fixed address
in the instruction. This is done by using File Select
Registers (FSRs) as pointers to the locations to be read
or written to. Since the FSRs are themselves located in
RAM as Special Function Registers, they can also be
directly manipulated under program control. This
makes FSRs very useful in implementing data
structures, such as tables and arrays in data memory.
The registers for Indirect Addressing are also
implemented with Indirect File Operands (INDFs) that
permit automatic manipulation of the pointer value with
auto-incrementing, auto-decrementing or offsetting
with another value. This allows for efficient code, using
loops, such as the example of clearing an entire RAM
bank in Example 5-5.
EXAMPLE 5-5:
NEXT
CONTINUE
LFSR
CLRF
BTFSS
BRA
INDIRECT ADDRESSING
FSR0, 100h ;
POSTINC0
FSR0H, 1
NEXT
HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
© 2007 Microchip Technology Inc.
; Clear INDF
; register then
; inc pointer
; All done with
; Bank1?
; NO, clear next
; YES, continue
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