EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 149

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

BusMstrArb
DS785UM1
31
15
Address:
Definition:
Bit Descriptions:
30
14
RSVD
29
13
Priority Number
28
12
0x8093_0054 - Read/Write
The Bus Master arbitration register (BusMstrArb) is used to configure the AHB
master priority order.
RSVD:
PRI_ORD:
PRI_CORE:
DMA_ENIRQ:
1
2
3
4
5
6
27
11
RSVD
(Reset value)
Raster Cursor
26
10
PRIOR 00
ARM920T
Raster
Table 5-6. Priority Order for AHB Arbiter
MAC
DMA
USB
Copyright 2007 Cirrus Logic
ENFIQ
MAC
25
9
Reserved. Unknown During Read.
Used to set the priority of the AHB arbiter. The priority
order is shown in
When this bit is set the Core will become highest priority
following a grant to one of the following: Raster, Raster
Cursor, MAC, USB and DMA. If the Core then requests the
bus, it is then placed in the priority order selected by
PRI_ORD after it is granted, until one of the above
masters is granted the bus, and is placed on top of the
priority scheme.
When set the arbiter will degrant DMA from the AHB bus
and will ignore subsequent requests from DMA if an IRQ is
active. When IRQ is cleared the DMA request is allowed
again. There is no impact on other masters. Reset to 0.
ENIRQ
MAC
24
8
RSVD
Raster Cursor
PRIOR 01
ARM920T
ENFIQ
Raster
USH
MAC
DMA
USB
23
7
ENIRQ
USH
22
Table
6
ENFIQ
DMA_
Raster Cursor
21
5-6. This field resets to 00.
5
PRIOR 10
ARM920T
Raster
DMA
MAC
USB
ENIRQ
DMA_
20
4
CORE
PRI
19
3
Raster Cursor
EP93xx User’s Guide
PRIOR 11
ARM920T
RSVD
Raster
System Controller
18
DMA
MAC
USB
2
17
1
PRI_ORD
16
5-23
0
5