EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 423

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

MAXCNTx
BASEx
DS785UM1
31
15
31
15
Address:
Definition:
Bit Descriptions:
Address:
Definition:
Bit Descriptions:
30
14
30
14
29
13
29
13
28
12
28
12
MAXCNT0: Channel Base Address + 0x0020 - Read/Write
MAXCNT1: Channel Base Address + 0x0030 - Read/Write
x = “0” or “1”. Maximum byte count for the buffer. Represents the double buffer
per channel. Only the low order 16 bits are used. Each MAXCNTx register
must be programmed before it’s corresponding BASEx register.
RSVD:
MAXCNTx:
BASE0: Channel Base Address + 0x0024 - Read/Write
BASE1: Channel Base Address + 0x0034 - Read/Write
Base address for the current and next DMA transfer.
BASEx:
27
11
27
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
Reserved. Unknown During Read.
Maximum byte count for the buffer.
x = “0” or “1”. Base address for the current and next DMA
transfer. Loaded with start address after enabling the DMA
Channel, the latter event required to take the Channel
State machine into the STALL state, the former event
required to enter the ON State.
24
24
8
MAXCNTx
8
BASEx
BASEx
RSVD
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
EP93xx User’s Guide
18
18
2
2
DMA Controller
17
17
1
1
10-29
16
16
0
0
10