EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 221
![IC ARM9 SOC PROCESSOR 208LQFP](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-CQZ
Manufacturer Part Number
EP9301-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-CQZ
Core Size
16/32-Bit
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-TQFP, 208-VQFP
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
166MHz
No. Of Timers
4
Digital Ic Case Style
TQFP
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1136
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUS
Quantity:
3 390
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUSLOGIC
Quantity:
20 000
Company:
Part Number:
EP9301-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
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VActiveStrtStop
DS785UM1
31
15
Address: 0x8003_0008
Default: 0x0000_0000
Definition: Vertical Active Start/Stop register
Bit Descriptions:
30
14
RSVD
RSVD
29
13
28
12
STRT:
RSVD:
STOP:
STRT:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
When the Vertical counter counts down to the written
STOP value, the VSYNC signal on the V_CSYNC pin will
go inactive if CSYNC = ‘0’ and SYNCEN = ‘1’ in the
VideoAttribs
timing diagrams shown in
Start - Read/Write
When the Vertical counter counts down to the written
STRT value, the VSYNC signal on the V_CSYNC pin will
go active if CSYNC = ‘0’ and SYNCEN = ‘1’ in the
VideoAttribs
Reserved - Unknown during read
Stop - Read/Write
The STOP value is the value of the Vertical down counter
at which the VACTIVE signal becomes inactive (stops).
This indicates the end of the active video portion for the
Vertical frame. Please refer to the video signalling timing
diagrams in
internal block signal. The active video interval is controlled
by the logical OR of VACTIVE and HACTIVE.
Start - Read/Write
The STRT value is the value of the Vertical down counter
at which the VACTIVE signal becomes active (starts). This
indicates the start of the active video portion for the
Vertical frame. Please refer to the video signalling timing
diagrams in
internal block signal. The active video interval is controlled
by the logical OR of VACTIVE and HACTIVE.
Raster Engine With Analog/LCD Integrated Timing and Interface
24
8
23
7
Figure 7-9
Figure 7-9
register. Please refer to the video signalling
register.
22
6
STOP
STRT
and
and
21
5
Figure 7-9
Figure
Figure
20
4
7-10. VACTIVE is an
7-10. VACTIVE is an
19
3
and
EP93xx User’s Guide
Figure
18
2
7-10.
17
1
16
7-39
0
7
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