EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 390

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

9
TXStsThrshld
9-88
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
31
15
Address:
Suggested Value:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x8001_00DC - Read/Write
0x0004_0002
0x0000_0000
Unchanged
Transmit Status Threshold register. The transmit status thresholds are used to
set a limit on the amount of transmit status which is held in the transmit status
FIFO before a bus request will be scheduled. When the number of words in
the FIFO exceeds the threshold value, the Descriptor Processor will schedule
a bus request to transfer status. The lower two bits of the thresholds are
always zero.
RSVD:
0:
TSHT:
TSST:
27
11
RSVD
RSVD
26
10
Copyright 2007 Cirrus Logic
25
9
The hard and soft threshold work in exactly the same
manner except one. The soft threshold will not cause a
bus request to be made if the bus is currently in use, but
only when it is deemed to be idle (no transfers for four
AHB clocks). The hard threshold takes effect immediately
regardless of the state of the bus. This operation allows for
more efficient use of the AHB bus by allowing smaller
transfers to take place when the bus is lightly loaded and
requesting larger transfers only when the bus is more
heavily loaded.
Reserved. Unknown During Read.
Must be written as “0”.
Transmit Status Hard Threshold.
Transmit Status Soft Threshold.
24
8
23
7
22
6
21
5
20
4
TSHT
TSST
19
3
18
2
17
0
1
0
DS785UM1
16
0
0
0