C8051T606-GM Silicon Laboratories Inc, C8051T606-GM Datasheet - Page 81

• Manufacturer Part Number: C8051T606-GM
• Description: IC 8051 MCU 1.5K-EEPROM 11-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T60xr

Specifications of C8051T606-GM

• Program Memory Type: OTP
• Program Memory Size: 1.5KB (1.5K x 8)
• Package / Case: 11-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 6
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051T606DK
• Minimum Operating Temperature: - 40 C
• Package: 11QFN EP
• Device Core: 8051
• Family Name: C8051T60x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1668 - CARD DAUGHTER QFN10 SOCKET336-1667 - CARD DAUGHTER MSOP SOCKET336-1666 - KIT DEVELOPMENT FOR C8051T606336-1404 - KIT DEV FOR C8051T60X MCU'S
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1662-5

C8051T600/1/2/3/4/5/6
17.1. MCU Interrupt Sources and Vectors
The C8051T600/1/2/3/4/5/6 MCUs support 12 interrupt sources. Software can simulate an interrupt by set-
ting an interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be
generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. MCU
interrupt sources, associated vector addresses, priority order and control bits are summarized in
Table 17.1. Refer to the datasheet section associated with a particular on-chip peripheral for information
regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
17.1.1. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low prior-
ity interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP or EIP1) used to configure
its priority level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with
the higher priority is serviced first. If both interrupts have the same priority level, a fixed priority order is
used to arbitrate, given in Table 17.1.
17.1.2. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5
system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the
ISR. If an interrupt is pending when a RETI is executed, a single instruction is executed before an LCALL
is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no
other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is
performing an RETI instruction followed by a DIV as the next instruction. In this case, the response time is
18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock
cycles to complete the DIV instruction and 4 clock cycles to execute the LCALL to the ISR. If the CPU is
executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the
current ISR completes, including the RETI and following instruction.
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