C8051F341-GQ Silicon Laboratories Inc, C8051F341-GQ Datasheet - Page 178

• Manufacturer Part Number: C8051F341-GQ
• Description: IC 8051 MCU FLASH 32K 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F34xr

Specifications of C8051F341-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-TQFP, 48-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 20x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SMBus/SPI/UART/USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F340DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 17-ch x 10-bit
• No. Of I/o's: 40
• Ram Memory Size: 2304Byte
• Cpu Speed: 48MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Package: 48TQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Data Rom Size: 128 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 17
• Height: 1 mm
• Length: 7 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1748 - ADAPTER TOOLSTICK FOR C8051F34X770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1452 - ADAPTER PROGRAM TOOLSTICK F340
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1299

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
16.10.3.Endpoint0 OUT Transactions
When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT
requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware will set
the OPRDY bit (E0CSR.0) to ‘1’ and generate an Endpoint0 interrupt. Following this interrupt, firmware
should unload the OUT packet from the Endpoint0 FIFO and set the SOPRDY bit (E0CSR.6) to ‘1’.
If the amount of data required for the transfer exceeds the maximum packet size for Endpoint0, the data
will be split into multiple packets. If the requested data is an integer multiple of the maximum packet size
for Endpoint0 (as reported to the host), the host will send a zero-length data packet signaling the end of the
transfer.
Upon reception of the first OUT token for a particular control transfer, Endpoint0 is said to be in Receive
Mode. In this mode, only OUT tokens should be sent by the host to Endpoint0. The SUEND bit (E0CSR.4)
is set to ‘1’ if a SETUP or IN token is received while Endpoint0 is in Receive Mode.
Endpoint0 will remain in Receive mode until:
Firmware should set the DATAEND bit (E0CSR.3) to ‘1’ when the expected amount of data has been
received. The SIE will transmit a STALL condition if the host sends an OUT packet after the DATAEND bit
has been set by firmware. An interrupt will be generated with the STSTL bit (E0CSR.2) set to ‘1’ after the
STALL is transmitted.
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1. The SIE receives a SETUP or IN token.
2. The host sends a packet less than the maximum Endpoint0 packet size.
3. The host sends a zero-length packet.
Rev. 1.3