C8051F341-GQ Silicon Laboratories Inc, C8051F341-GQ Datasheet - Page 189
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C8051F341-GQ
Manufacturer Part Number
C8051F341-GQ
Description
IC 8051 MCU FLASH 32K 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Datasheets
1.C8051F349-GQ.pdf
(276 pages)
2.C8051F341-GQ.pdf
(1 pages)
3.C8051F347-GQ.pdf
(296 pages)
Specifications of C8051F341-GQ
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
48MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
40
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 20x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
I2C/SMBus/SPI/UART/USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
On-chip Adc
17-ch x 10-bit
No. Of I/o's
40
Ram Memory Size
2304Byte
Cpu Speed
48MHz
No. Of Timers
4
Rohs Compliant
Yes
Package
48TQFP
Device Core
8051
Family Name
C8051F34x
Maximum Speed
48 MHz
Data Rom Size
128 B
A/d Bit Size
10 bit
A/d Channels Available
17
Height
1 mm
Length
7 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
7 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1748 - ADAPTER TOOLSTICK FOR C8051F34X770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1452 - ADAPTER PROGRAM TOOLSTICK F340
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1299
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F341-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F341-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
17.1. Supporting Documents
It is assumed the reader is familiar with or has access to the following supporting documents:
17.2. SMBus Configuration
Figure 17.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage
between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-direc-
tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage
through a pull-up resistor or similar circuit. Every device connected to the bus must have an open-drain or
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when
the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.
17.3. SMBus Operation
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme
is employed with a single master always winning the arbitration. Note that it is not necessary to specify one
device as the Master in a system; any device who transmits a START and a slave address becomes the
master for the duration of that transfer.
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7-1: 7-bit
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Each byte that is
received (by a master or slave) must be acknowledged (ACK) with a low SDA during a high SCL (see
Figure 17.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowl-
edge), which is a high SDA during a high SCL.
1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor.
2. The I2C-Bus Specification -- Version 2.0, Philips Semiconductor.
3. System Management Bus Specification -- Version 1.1, SBS Implementers Forum.
VDD = 5V
Figure 17.2. Typical SMBus Configuration
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
VDD = 3V
Master
Device
Rev. 1.3
VDD = 5V
Device 1
Slave
VDD = 3V
Device 2
Slave
SDA
SCL
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