HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 153

• Manufacturer Part Number: HD6417041AVF16V
• Description: IC SUPERH MCU ROMLESS 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD6417041AVF16V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.1.6
Description: Reads the T bit, and conditionally branches. If T = 0, it branches to the branch
destination address. If T = 1, BF executes the next instruction. The branch destination is an
address specified by PC + displacement. However, in this case it is used for address calculation.
The PC is the address 4 bytes after this instruction. The 8-bit displacement is sign-extended and
doubled. Consequently, the relative interval from the branch destination is –256 to +254 bytes. If
the displacement is too short to reach the branch destination, use BF with the BRA instruction or
the like.
Note: When branching, three cycles; when not branching, one cycle.
Operation:
Format
BF
BF(long d)/* BF disp */
{
}
long disp;
if ((d&0x80)==0) disp=(0x000000FF & (long)d);
else disp=(0xFFFFFF00 | (long)d);
if (T==0) PC=PC+(disp<<1);
else PC+=2;
label When T = 0,
BF (Branch if False): Branch Instruction
Abstract
disp
When T = 1, nop
2 + PC
PC;
Code
10001011dddddddd 3/1
Rev. 5.00 Jun 30, 2004 page 137 of 512
Cycle T Bit SH-1 SH-2
Section 6 Instruction Descriptions
—
REJ09B0171-0500O
Instructions
Applicable
SH-
DSP