M30879FLFP#U3 Renesas Electronics America, M30879FLFP#U3 Datasheet
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M30879FLFP#U3
Specifications of M30879FLFP#U3
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M30879FLFP#U3 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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M32C/87 Group (M32C/87, 16/ M32C/87A, M32C/87B) 32 Hardware Manual RENESAS MCU M16C FAMILY / M32C/80 SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU intended for users designing application systems incorporating ...
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Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in ...
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Register Notation The symbols and terms used in register diagrams are described below. XXX Register Bit Symbol XXX0 XXX1 (b2) (b3) XXX4 XXX5 XXX6 XXX7 *1 Blank: Set to 0 ...
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List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO All trademarks and registered trademarks are the property of their respective owners. IEBus is ...
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Special Function Register (SFR) Page Reference ............................................................................... Overview ......................................................................................................................................... 1 1.1 Features ..................................................................................................................................................... 1 1.1.1 Applications .......................................................................................................................................... 1 1.1.2 Specifications ........................................................................................................................................ 2 1.2 Product List .......................................................................................................................................... 6 1.3 Block Diagram .......................................................................................................................................... 8 1.4 Pin Assignments ........................................................................................................................................ ...
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Selecting External Address Bus ......................................................................................................... 64 8.1.2 Selecting External Data Bus ............................................................................................................... 64 8.1.3 Selecting Separate Bus/Multiplexed Bus ........................................................................................... 64 8.2 Bus Control ............................................................................................................................................. 66 8.2.1 Address Bus and Data Bus ................................................................................................................. 66 8.2.2 Chip-Select Output ............................................................................................................................. 66 8.2.3 ...
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Relocatable Vector Table ................................................................................................................. 110 11.6 Interrupt Request Acknowledgement .................................................................................................... 113 11.6.1 I Flag and IPL ................................................................................................................................... 113 11.6.2 Interrupt Control Registers and RLVL Register ............................................................................... 113 11.6.3 Interrupt Sequence ............................................................................................................................ 117 11.6.4 Interrupt Response Time .................................................................................................................. 118 11.6.5 ...
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Execution Time ..................................................................................................................................... 158 15. Timers ......................................................................................................................................... 159 15.1 Timer A ................................................................................................................................................. 161 15.1.1 Timer Mode ...................................................................................................................................... 173 15.1.2 Event Counter Mode ......................................................................................................................... 174 15.1.3 One-Shot Timer Mode ...................................................................................................................... 179 15.1.4 Pulse Width Modulation Mode ......................................................................................................... 181 15.2 Timer ...
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External Operating Amplifier (Op-Amp) Connection Mode ........................................................... 310 18.2.7 Power Consumption Reduce Function ............................................................................................. 310 18.3 Read from the AD0i Register ( .............................................................................................. 311 18.4 Output Impedance of Sensor Equivalent Circuit under A/D Conversion ............................................. ...
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CANi Single-Shot Status Register (CiSSSTR Register ................................................... 430 23.1.19 CANi Global Mask Register, CANi Local Mask Register A, and CANi Local Mask Register B (CiGMRk, CiLMARk, and CiLMBRk Registers 0, ...
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Electrical Characteristics ............................................................................................................. 519 28. Usage Notes ............................................................................................................................... 556 28.1 Power Supply ........................................................................................................................................ 556 28.1.1 Power-on ........................................................................................................................................... 556 28.1.2 Power Supply Ripple ........................................................................................................................ 557 28.1.3 Noise ................................................................................................................................................. 557 28.2 Special Function Registers (SFRs) ........................................................................................................ 558 28.2.1 100 Pin-Package ............................................................................................................................... ...
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Boot Mode ........................................................................................................................................ 580 28.16.9 Writing Command and Data ............................................................................................................. 580 28.16.10 Block Erase ...................................................................................................................................... 580 28.16.11 Wait Mode ....................................................................................................................................... 580 28.16.12 Stop Mode ........................................................................................................................................ 580 28.16.13 Low-Power Consumption Mode and On-Chip Oscillator Low-Power Consumption Mode ........... 580 28.17 ...
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Special Function Register (SFR) Page Reference Address Register 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 0005h Processor Mode Register 1 0006h System Clock Control Register 0 0007h System Clock Control Register 1 0008h 0009h Address Match Interrupt Enable ...
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Special Function Register (SFR) Page Reference Address Register II/O Interrupt Control Register 1/ 0095h CAN1 Interrupt Control Register 1 0096h Timer B2 Interrupt Control Register 0097h II/O Interrupt Control Register 3 0098h Timer B4 Interrupt Control Register II/O Interrupt Control ...
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Special Function Register (SFR) Page Reference Address Register 0140h Group 2 Waveform Generation Control Register 0 0141h 0142h Group 2 Waveform Generation Control Register 1 0143h 0144h Group 2 Waveform Generation Control Register 2 0145h 0146h Group 2 Waveform Generation ...
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Special Function Register (SFR) Page Reference . Address Register 0200h CAN0 Control Register 0 0201h 0202h CAN0 Status Register 0203h 0204h CAN0 Extended ID Register 0205h 0206h CAN0 Configuration Register 0207h 0208h CAN0 Time Stamp Register 0209h 020Ah CAN0 Transmit ...
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Special Function Register (SFR) Page Reference Address Register 0290h CAN1 Slot Interrupt Mask Register 0291h 0292h 0293h 0294h CAN1 Error Interrupt Mask Register 0295h CAN1 Error Interrupt Status Register 0296h CAN1 Error Source Register 0297h CAN1 Baud Rate Prescaler 0298h ...
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Special Function Register (SFR) Page Reference Address Register 0320h 0321h 0322h 0323h 0324h UART3 Special Mode Register 4 0325h UART3 Special Mode Register 3 0326h UART3 Special Mode Register 2 0327h UART3 Special Mode Register 0328h UART3 Transmit/Receive Mode Register ...
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Special Function Register (SFR) Page Reference .. Address Register 03C0h Port P6 Register 03C1h Port P7 Register 03C2h Port P6 Direction Register 03C3h Port P7 Direction Register 03C4h Port P8 Register 03C5h Port P9 Register 03C6h Port P8 Direction Register ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) RENESAS MCU 1. Overview 1.1 Features The M32C/87 Group (M32C/87, M32C/87A, M32C/87B single-chip control MCU, fabricated using high- performance silicon gate CMOS technology, embedding the M32C/80 Series CPU core. The M32C/87 Group (M32C/ ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 1.1.2 Specifications Tables 1.1 to 1.4 list the specifications of the M32C/87 Group (M32C/87, M32C/87A, M32C/87B). Table 1.1 Specifications (144-Pin Package) (1/2) Item Function CPU Central processing unit Memory ROM, RAM, data flash Power Supply ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.2 Specifications (144-Pin Package) (2/2) Item Function Serial Interface UART0 to UART4 UART5, UART6 A/D Converter D/A Converter CRC Calculation Circuit X/Y Converter Intelligent I/O ROM Correction Function CAN modules I/O Ports Programmable I/O ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.3 Specifications (100-Pin Package) (1/2) Item Function CPU Central processing unit Memory ROM, RAM, data flash Power Supply Voltage Detection External Bus Bus/memory Expansion expansion function Clock Clock generation circuits Interrupts Watchdog Timer DMA ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.4 Specifications (100-Pin Package) (2/2) Item Function Serial Interface UART0 to UART4 UART5 A/D Converter D/A Converter CRC Calculation Circuit X/Y Converter Intelligent I/O ROM Correction Function CAN modules I/O Ports Programmable I/O ports ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 1.2 Product List Tables 1.5 to 1.7 list product information. Figure 1.1 shows product numbering system. Table 1.5 M32C/87 Group (1) (M32C/87: 2-channel CAN module) Part Number M3087BFLGP PLQP0144KA-A (144P6Q-A) M30879FLFP PRQP0100JB-A (100P6S-A) M30879FLGP PLQP0100KB-A ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.7 M32C/87 Group (3) (M32C/87B: no CAN module) Part Number M3087BFLBGP PLQP0144KA-A (144P6Q-A) M30879FLBFP PRQP0100JB-A (100P6S-A) M30879FLBGP PLQP0100KB-A (100P6Q-A) M3087BFKBGP PLQP0144KA-A (144P6Q-A) M30879FKBGP PLQP0100KB-A (100P6Q-A) M30878FJBGP PLQP0144KA-A (144P6Q-A) M30876FJBGP PLQP0100KB-A (100P6Q-A) M30875FHBGP PLQP0144KA-A (144P6Q-A) ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 1.3 Block Diagram Figure 1.2 shows a block diagram of the M32C/87 Group (M32C/87, M32C/87A, M32C/87B). 8 Port P0 Port P1 Internal peripheral functions Timers (16 bits) Output (timer A): 5 Input (timer B): 6 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 1.4 Pin Assignments Figures 1.3 to 1.5 show pin assignments (top view P1_0 109 D7 / AN0_7 / P0_7 110 D6 / AN0_6 / P0_6 111 D5 / AN0_5 / P0_5 112 D4 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.8 144-Pin Package List of Pin Names (1/4) Pin Control Interrupt Port No. Pin Pin 1 P9_6 2 P9_5 3 P9_4 4 P9_3 5 P9_2 6 P9_1 7 P9_0 8 P14_6 INT8 9 P14_5 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.9 144-Pin Package List of Pin Names (2/4) Pin Control Interrupt Port No. Pin Pin 41 VSS 42 P6_5 43 P6_4 44 P6_3 45 P6_2 46 P6_1 47 P6_0 48 P13_7 49 P13_6 50 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.10 144-Pin Package List of Pin Names (3/4) Pin Control Interrupt Port No. Pin Pin 81 P3_5 82 P3_4 83 P3_3 84 P3_2 85 P3_1 86 P12_4 87 P12_3 88 P12_2 89 P12_1 90 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.11 144-Pin Package List of Pin Names (4/4) Pin Control Interrupt Port No. Pin Pin 121 P0_1 122 P0_0 123 P15_7 124 P15_6 125 P15_5 126 P15_4 127 P15_3 128 P15_2 129 P15_1 130 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B AN0_7 / P0_7 D6 / AN0_6 / P0_6 D5 / AN0_5 / P0_5 D4 / AN0_4 / P0_4 D3 / AN0_3 / P0_3 D2 / AN0_2 / P0_2 D1 / AN0_1 / P0_1 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B P1_1 D8 / P1_0 D7 / AN0_7 / P0_7 D6 / AN0_6 / P0_6 D5 / AN0_5 / P0_5 D4 / AN0_4 / P0_4 D3 / AN0_3 / P0_3 D2 / AN0_2 / ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.12 100-Pin Package List of Pin Names (1/3) Pin No. Control Interrupt Port Pin Pin P9_6 2 100 P9_5 3 1 P9_4 4 2 P9_3 5 3 P9_2 6 4 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.13 100-Pin Package List of Pin Names (2/3) Pin No. Control Interrupt Port Pin Pin P5_5 42 40 P5_4 43 41 CLKOUT P5_3 44 42 P5_2 45 43 P5_1 46 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.14 100-Pin Package List of Pin Names (3/3) Pin No. Control Interrupt Port Pin Pin P1_7 INT5 74 72 P1_6 INT4 75 73 P1_5 INT3 76 74 P1_4 77 75 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 1.5 Pin Functions Table 1.15 Pin Functions (100-Pin and 144-Pin Packages) (1/4) Type Symbol Power supply VCC1,VCC2 VSS Analog power AVCC supply input AVSS Reset input RESET CNVSS CNVSS External data BYTE bus width select ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.16 Pin Functions (100-Pin and 144-Pin Packages) (2/4) Type Symbol Main clock XIN input Main clock XOUT output Sub clock XCIN input Sub clock XCOUT output BCLK output BCLK Clock output CLKOUT INT interrupt ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.17 Pin Functions (100-Pin and 144-Pin Package) (3/4) Type Symbol Intelligent I/O INPC1_0 to INPC1_3 INPC1_4 to INPC1_7 OUTC1_0 to OUTC1_3 OUTC1_4 to OUTC1_7 OUTC2_0 to OUTC2_2 ISCLK0 ISCLK1, ISCLK2 ISRXD0 ISRXD1, ISRXD2 ISTXD0 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.18 Pin Functions (100-Pin and 144-Pin Package) (4/4) Type Symbol I/O port P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7 P6_0 to P6_7, P7_0 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The register bank is comprised of eight registers (R0, R1, R2, R3, A0, A1, SB, and FB) out of 28 CPU registers. There are ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 2.1 General Registers 2.1.1 Data Registers (R0, R1, R2, and R3) R0, R1, R2, and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order (R0H/R1H) and ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 2.1.8.7 Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0 and enabled when it is set to 1. The I flag becomes 0 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 3. Memory Figure 3.1 shows a memory map of the M32C/87 Group (M32C/87, M32C/87A, M32C/87B). The M32C/87 Group (M32C/87, M32C/87A, M32C/87B) has 16-Mbyte address space from addresses 000000h to FFFFFFh. The internal ROM is allocated ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 4. Special Function Registers (SFRs) Special Function Registers (SFRs) are the control registers of peripheral functions. Tables 4.1 to 4.20 list SFR address maps. Table 4.1 SFR Address Map (1/20) Address 0000h 0001h 0002h 0003h ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.2 SFR Address Map (2/20) Address 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h Address Match Interrupt Register 6 003Ah 003Bh 003Ch 003Dh Address Match Interrupt Register 7 003Eh 003Fh 0040h 0041h ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.3 SFR Address Map (3/20) Address 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h DMA0 Interrupt Control Register 0069h Timer B5 Interrupt Control Register 006Ah DMA2 Interrupt Control Register 006Bh UART2 Receive/ACK Interrupt ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.4 SFR Address Map (4/20) Address 0090h UART0 Transmit/NACK Interrupt Control Register 0091h UART1/UART4 Bus Conflict Detection Interrupt Control Register 0092h UART1 Transmit/NACK Interrupt Control Register 0093h Key Input Interrupt Control Register 0094h Timer ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.5 SFR Address Map (5/20) Address 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h Group 0 SI/O Receive Buffer Register 00E9h 00EAh Group 0 Transmit Buffer/Receive Data Register 00EBh 00ECh Group 0 Receive ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.6 SFR Address Map (6/20) Address 011Ah Group 1 Time Measurement Control Register 2 011Bh Group 1 Time Measurement Control Register 3 011Ch Group 1 Time Measurement Control Register 4 011Dh Group 1 Time ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.7 SFR Address Map (7/20) Address 0150h Group 2 Waveform Generation Control Register 0 0151h Group 2 Waveform Generation Control Register 1 0152h Group 2 Waveform Generation Control Register 2 0153h Group 2 Waveform ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.8 SFR Address Map (8/20) Address 01C0h UART5 Transmit/Receive Mode Register 01C1h UART5 Baud Rate Register 01C2h UART5 Transmit Buffer Register 01C3h 01C4h UART5 Transmit/Receive Control Register 0 01C5h UART5 Transmit/Receive Control Register 1 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.9 SFR Address Map (9/20) Address 01F0h CAN0 Message Slot Buffer 1 Standard ID0 01F1h CAN0 Message Slot Buffer 1 Standard ID1 01F2h CAN0 Message Slot Buffer 1 Extended ID0 01F3h CAN0 Message Slot ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.10 SFR Address Map (10/20) Address 0220h CAN0 Single Shot Control Register 0221h 0222h 0223h 0224h CAN0 Single Shot Status Register 0225h 0226h 0227h 0228h CAN0 Global Mask Register Standard ID0 0229h CAN0 Global ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.11 SFR Address Map (11/20) Address 0250h CAN1 Slot Buffer Select Register 0251h CAN1 Control Register 1 0252h CAN1 Sleep Control Register 0253h 0254h CAN1 Acceptance Filter Support Register 0255h 0256h 0257h 0258h 0259h ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.12 SFR Address Map (12/20) Address 0280h CAN1 Control Register 0 0281h 0282h CAN1 Status Register 0283h 0284h CAN1 Extended ID Register 0285h 0286h CAN1 Configuration Register 0287h 0288h CAN1 Time Stamp Register 0289h ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.13 SFR Address Map (13/20) Address CAN1 Message Slot 0 Control Register / 02B0h CAN1 Local Mask Register A Standard ID0 CAN1 Message Slot 1 Control Register / 02B1h CAN1 Local Mask Register A ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.14 SFR Address Map (14/20) Address 02C0h X0 Register, Y0 Register 02C1h 02C2h X1 Register, Y1 Register 02C3h 02C4h X2 Register, Y2 Register 02C5h 02C6h X3 Register, Y3 Register 02C7h 02C8h X4 Register, Y4 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.15 SFR Address Map (15/20) Address 02F0h 02F1h 02F2h 02F3h 02F4h UART4 Special Mode Register 4 02F5h UART4 Special Mode Register 3 02F6h UART4 Special Mode Register 2 02F7h UART4 Special Mode Register 02F8h ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.16 SFR Address Map (16/20) Address 0320h 0321h 0322h 0323h 0324h UART3 Special Mode Register 4 0325h UART3 Special Mode Register 3 0326h UART3 Special Mode Register 2 0327h UART3 Special Mode Register 0328h ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.17 SFR Address Map (17/20) Address 0350h Timer B0 Register 0351h 0352h Timer B1 Register 0353h 0354h Timer B2 Register 0355h 0356h Timer A0 Mode Register 0357h Timer A1 Mode Register 0358h Timer A2 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.18 SFR Address Map (18/20) Address 0380h A/D0 Register 0 0381h 0382h A/D0 Register 1 0383h 0384h A/D0 Register 2 0385h 0386h A/D0 Register 3 0387h 0388h A/D0 Register 4 0389h 038Ah A/D0 Register ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.19 SFR Address Map (19/20) Address 03A0h Function Select Register A8 03A1h Function Select Register A9 03A2h 03A3h Function Select Register B9 03A4h Function Select Register E2 03A5h 03A6h 03A7h Function Select Register D1 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 4.20 SFR Address Map (20/20) Address 03D0h Port P14 Register (1) 03D1h Port P15 Register (1) 03D2h Port P14 Direction Register 03D3h Port P15 Direction Register 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh Pull-Up ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5. Reset Hardware reset 1, hardware reset 2 (Vdet3 detection function), software reset and watchdog timer reset are implemented to reset the MCU. 5.1 Hardware Reset 1 Pins, CPU, and SFRs are reset by using ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) VCC1, VCC2 XIN Td(P- more is required RESET BCLK Microprocessor mode BYTE = "H" Address “H” A23 “L” “H” RD “L” “H” WR “L” Microprocessor mode BYTE = "L" Address “H” A23 “L” ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 5.1 Pin States while RESET Pin is Held “L” Single-Chip Mode Pin Name CNVSS = “L” P0 Input port (high-impedance) P1 Input port (high-impedance Input port (high-impedance) P5_0 Input port (high-impedance) ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 5.5 Internal Registers Figure 5.3 shows CPU register states after reset. Refer to 4. Special Function Registers (SFRs) for SFR states after reset after reset X: Undefined after reset General registers b15 b15 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 6. Power Supply Voltage Detection Function The power supply voltage detection function has the Vdet3 detection function, Vdet4 detection function, and cold start/warm start determination function. The Vdet3 detection function and Vdet4 detection function detect ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Voltage Detection Register 1 Symbol VCR1 Bit Symbol − (b2-b0) VC13 − (b7-b4) NOTE: 1. The VC13 bit is enabled ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Vdet4 Detection Interrupt Register Symbol D4INT Bit Symbol D40 D41 D42 D43 DF0 DF1 − (b7-b6) NOTES: 1. Set the D4INT register after the PRC3 bit in ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Watchdog Timer Control Register Symbol WDC Bit Symbol − (b4-b0) WDC5 − (b6) WDC7 NOTE: 1. The WDC5 bit is 0 after power-on. It can be ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 6.1 Vdet3 Detection Function The hardware reset 2 is performed if the voltage applied to the VCC1 pin drops to Vdet3 (V) or below. Set the VC26 bit in the VCR2 register ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 6.2 Vdet4 Detection Function Vdet4 detection interrupt is generated if the voltage applied to the VCC1 pin crosses the Vdet4 (V) level, either by dropping below or by rising above Vdet4. Set the VC27 bit ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Voltage applied to VCC1 Vdet4 (V) 3 (V) “H” RESET “L” 1 VC27 bit 0 1 VC13 bit 0 <When wait mode/stop mode is not used> Sampling period “H” Output from digital filter “L” 1 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 6.2.1 Usage Notes on Vdet4 Detection Interrupt When all the conditions below are met, the Vdet4 detection interrupt is generated and the MCU exits wait mode as soon as the WAIT instruction is executed or ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 7. Processor Mode 7.1 Processor Mode Single-chip mode, memory expansion mode, microprocessor mode, or boot mode can be selected as the processor mode. Table 7.1 lists the features of the processor mode. Table 7.1 Processor ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Processor Mode Register Symbol 0 PM0 Bit Symbol PM00 PM01 PM02 PM03 PM04 PM05 − (b6) PM07 NOTES: 1. Set the PM0 register after the PRC1 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Processor Mode Register 1 Symbol PM1 Bit Symbol PM10 PM11 PM12 PM13 PM14 PM15 − (b7-b6) NOTES: 1. Set the PM1 register after the PRC1 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Single-chip mode 000000h SFR 000400h Internal RAM Reserved 00F000h Block A (3) 010000h 100000h 200000h 300000h 400000h Not used C00000h D00000h E00000h F00000h Internal ROM (4) FFFFFFh 000000h 000400h 010000h 100000h CS area controlled by ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 8. Bus In memory expansion mode or microprocessor mode, the following pins become bus control pins D15 A22, A23, CS0 to CS3, WRL/WR, WRH/BHE, RD, CLKOUT/BCLK/ALE, HLDA/ALE, HOLD, ALE, and RDY. ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 8.1.1 Selecting External Address Bus The number of external address bus pins, the number of chip-select pins, and chip-select-assigned address space (CS area) vary in each external space mode. Bits PM11 and PM10 in the ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 8.3 Processor Mode and Pin Function Processor Single-chip Mode Mode PM05 and 00b PM04 bits (Multiplexed bus not used) (1) setting Data bus width Access all external spaces with 8-bit data bus P0_0 to ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 8.2 Bus Control Described below are the signals required to access external devices and the bus timing. The signals are available in memory expansion mode and microprocessor mode only. 8.2.1 Address Bus and Data Bus ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Example 1: After accessing the external space, both address bus and chip-select output change When the MCU accesses the external space j specified by another chip-select output in the next cycle after having accessed the ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 8.2.3 Read/Write Output Signals When using a 16-bit data bus, the PM02 bit in the PM0 register selects either a combination of the “RD, WR, and BHE” outputs or the “RD, WRL, and WRH” outputs ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 8.2.4 Bus Timing Software wait states for the internal ROM and internal RAM can be set using the PM12 bit in the PM1 register, for the SFR area using the PM13 bit, and for external ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 8.6 Software Wait State and Bus Cycle Space External Bus Status SFR area − Internal ROM/ − RAM Separate bus External memory Multiplexed bus NOTE: 1. Set the PM13 bit to 1 before accessing ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) • Bus cycle 1 φ φ φ 1 bus cycle = 2 BCLK Address CSi (Note 1) Read data RD Write data WR, WRL, WRH • Bus cycle 1 φ φ ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Bus cycle • φ φ 1 bus cycle = 4 BCLK Address CSi Read data RD Write data WR, WRL, WRH Bus cycle • φ φ 1 bus cycle ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Bus cycle • φ φ BCLK Address CSi Read data RD Write data WR, WRL, WRH Bus cycle • φ φ BCLK Address CSi Read data RD Write data ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) • Bus cycle φ φ 1 bus cycle = 4 BCLK CSi Read data LA RD Write data LA WR (WRL) ALE • Bus cycle φ φ BCLK CSi ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) • Bus cycle φ φ BCLK CSi Read data LA RD Write data LA WR (WRL) ALE • Bus cycle φ φ BCLK CSi Read data LA RD Write ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 8.2.4.1 Bus Cycle with Recovery Cycle Inserted The EWCRi6 bit in the EWCRi register ( determines whether the recovery cycle is inserted or not. Address output or data output is held ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 8.2.5 ALE Output The ALE output signal is provided for the external devices to latch the address when using the multiplexed bus. Latch the address at the falling edge of the ALE output. Bits PM15 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) - Separate bus (bus cycle is 1 BCLK CSi (1) RD RDY tsu(RDY-BCLK) Timing to input RDY signal Wait states inserted by RDY input tsu(RDY-BCLK): RDY input setup time ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 8.2.8 External Bus States when Accessing Internal Space Table 8.9 lists external bus states when the internal space is accessed. Table 8.9 External Bus States when Accessing Internal Space Item A0 to A22, A23 D0 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 9. Clock Generation Circuits 9.1 Types of the Clock Generation Circuit The MCU has four on-chip clock generation circuits to generate system clock signals. • Main clock oscillation circuit • Sub clock oscillation circuit • ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Interrupt priority level Logic 1 write signal decision output to CM10 bit Vdet4 detection interrupt signal NMI WAIT instruction RESET Main clock oscillation circuit XIN XOUT CM05 Stop mode PM26 Clock stop signal in wait ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) System Clock Control Register Symbol CM0 Bit Symbol CM00 CM01 CM02 CM03 CM04 CM05 CM06 CM07 NOTES: 1. Set the CM0 register after the PRC0 bit ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) System Clock Control Register 1 Symbol CM1 Bit Symbol CM10 − (b4-b1) − (b5) − (b6) CM17 NOTES: 1. Set the ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Main Clock Division Register Symbol MCD Bit Symbol MCD0 MCD1 MCD2 MCD3 MCD4 − (b7-b5) NOTES: 1. Set the MCD register after the PRC0 bit in the ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Oscillation Stop Detection Register Symbol CM2 Bit Symbol CM20 CM21 CM22 CM23 − (b7-b4) NOTES: 1. Set the CM2 register after the PRC0 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) PLL Control Register 0 Symbol PLC0 Bit Symbol PLC00 PLC01 PLC02 − (b3) − (b4) − (b5) − (b6) PLC07 NOTES: 1. Set the ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Processor Mode Register 2 Symbol PM2 Bit Symbol − (b0) PM21 PM22 − (b3) PM24 PM25 PM26 PM27 NOTES: 1. Set the PM2 register after ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Count Source Prescaler Register Symbol TCSPR Bit Symbol CNT0 CNT1 CNT2 CNT3 − (b6-b4) CST NOTES: 1. Set bits CNT3 to CNT0 after the CST bit is ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 9.1.1 Main Clock Main clock oscillation circuit generates the main clock. The main clock is used as the clock source for the CPU clock and peripheral function clocks. The main clock oscillation circuit is configured ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 9.1.2 Sub Clock Sub clock oscillation circuit generates the sub clock. The sub clock is used as the clock source for the CPU clock and for timer A and timer B. fC, which has the ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 9.1.3 On-Chip Oscillator Clock On-chip oscillator generates the 1-MHz on-chip oscillator clock. The on-chip oscillator clock is used as the clock source for the CPU clock and peripheral function clocks. The on-chip oscillator clock is ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Start Read the CM23 bit in the CM2 register 1 (Main clock stops) Verified several times? PRCR register: PRC0 bit = 1 MCD register: bits MCD4 to MCD0 = 01000b CM2 register: CM22 bit = ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 9.1.4 PLL Clock The PLL frequency synthesizer generates the PLL clock by multiplying the main clock. The PLL clock can be used as the clock source for the CPU clock and peripheral function clocks. The ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 9.2 CPU Clock and BCLK The CPU clock is used to operate the CPU and also used as the count source for the watchdog timer. After reset, the CPU clock is the main clock divided ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 9.4 Clock Output Function The CLKOUT pin outputs fC, f8, or f32. The BCLK clock, which has the same frequency as the CPU clock, can be output from the BCLK pin in memory expansion mode ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 9.5 Power Consumption Control The power consumption control is enabled by controlling a CPU clock frequency. The higher the CPU clock frequency is, the more the processing power is available. The lower the CPU clock ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 9.5.1.1 Main Clock Mode The main clock divided by 1 (no division 10, 12, 14 used as the source for the CPU clock. The main clock is ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 9.6 Operation Mode Setting CPU Clock Operating Mode Source Main clock mode Main clock Main clock direct (2) mode PLL clock PLL mode Low-speed mode Sub clock Low power consumption mode On-chip oscillator mode ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Start (1) Initial setting RLVL register: bits RLVL2 to RLVL0 = 7 Set an interrupt priority level of each interrupt (2) Before entering wait mode I flag = 0 Set the interrupt priority level (ILVL2 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 9.5.2.3 Pin States in Wait Mode Table 9.7 lists pin states in wait mode. Table 9.7 Pin States in Wait Mode Pin Address bus, data bus, CS0 to CS3, BHE RD, WR, WRL, WRH HLDA, ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 9.8 Interrupts to Exit Wait Mode and Usage Conditions Interrupt NMI interrupt Vdet4 detection interrupt Serial interface interrupt Key input interrupt A/D conversion interrupt Timer A interrupt Timer B interrupt INT interrupt CAN interrupt ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Start (1) Initial setting RLVL register: bits RLVL2 to RLVL0 = 7 Set an interrupt priority level of each interrupt (2) Before entering stop mode I flag = 0 Set the interrupt priority level (ILVL2 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 9.5.3.2 Pin States in Stop Mode Table 9.9 lists pin states in stop mode. Table 9.9 Pin States in Stop Mode Pin Address Bus, Data Bus, CS0 to CS3, BHE RD, WR, WRL, WRH HLDA, ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 9.6 System Clock Protect Function The system clock protect function prohibits the clock setting from being rewritten in order to prevent the CPU clock source from being changed when a program goes out of control. ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 10. Protection The function protects important registers from being inadvertently overwritten in case of a program crash. Figure 10.1 shows the PRCR register. The PRC2 bit in the PRCR register becomes 0 (write disable) by ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 11. Interrupts 11.1 Types of Interrupts Figure 11.1 shows the types of interrupts. Software (Non-maskable interrupts) Interrupts Hardware NOTES: 1. Peripheral function interrupts are generated by the on-chip peripheral functions in the MCU ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 11.2 Software Interrupts Software interrupts occur when particular instructions are executed. Software interrupts are non-maskable. 11.2.1 Undefined Instruction Interrupt The undefined instruction interrupt occurs when the UND instruction is executed. 11.2.2 Overflow Interrupt The overflow ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 11.3 Hardware Interrupts Special interrupts and peripheral function interrupts are available as hardware interrupts. 11.3.1 Special Interrupts Special interrupts are non-maskable. 11.3.1.1 NMI Interrupt The NMI interrupt occurs when a signal applied to the NMI ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 11.4 High-Speed Interrupt The high-speed interrupt executes an interrupt sequence in five cycles and returns from the interrupt routine in three cycles. When the FSIT bit in the RLVL register is set to 1 (interrupt ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 11.5 Interrupts and Interrupt Vectors There are four bytes in each interrupt vector. Set the starting address of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, an interrupt routine is ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 11.2 Relocatable Vector Tables (1/2) Interrupt Source (2) BRK instruction Reserved space DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 (3) UART0 transmission, NACK (3) UART0 reception, ACK ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 11.3 Relocatable Vector Tables (2/2) Interrupt Source Bus conflict detection, Start condition detection/ Stop condition detection (3) (UART2) Bus conflict detection, Start condition detection/ Stop condition detection (4) (UART3 or UART0) Bus conflict detection, ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 11.6 Interrupt Request Acknowledgement Software interrupts occur when their corresponding instructions are executed. The INTO instruction, however, requires the O flag in the FLG register Special interrupts occur when their corresponding interrupt ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Interrupt Control Register Symbol TA0IC to TA4IC TB0IC to TB5IC S0TIC to S4TIC S0RIC to S4RIC BCN0IC to BCN4IC DM0IC to DM3IC AD0IC KUPIC IIO0IC to IIO5IC ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Interrupt Control Register Symbol INT0IC to INT2IC INT3IC to INT5IC Bit Symbol ILVL0 ILVL1 ILVL2 IR POL LVS − (b7-b6) NOTES: 1. When a 16-bit data bus ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Exit Priority Register Symbol RLVL Bit Symbol RLVL0 RLVL1 RLVL2 FSIT − (b4) DMAII − (b7-b6) NOTES: 1. The MCU exits stop or wait mode when an ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 11.6.3 Interrupt Sequence The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine execution. When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt priority ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 11.6.4 Interrupt Response Time Figure 11.7 shows the interrupt response time. Interrupt response time is the period between an interrupt request generation and the end of an interrupt sequence. Interrupt response time is divided into ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 11.6.5 IPL Change when Interrupt Request is Acknowledged When a peripheral function interrupt request is acknowledged, the priority level for the acknowledged interrupt becomes the IPL level in the flag register. Software interrupts and special ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 11.6.7 Returning from Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the values of the FLG register and PC, which have been saved to the stack before the ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) High Interrupt priority level DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 UART0 transmission/NACK UART0 reception/ACK UART1 transmission/NACK UART1 reception/ACK Timer B0 Timer B1 Timer B2 Timer B3 Timer ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 11.7 INT Interrupt External input to pins INT0 to INT8 generates the INT0 to INT8 interrupt. INT0 to INT5 interrupts can select either edge sensitive, which the rising/falling edge triggers an interrupt request, or level ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) < Procedure for Edge Sensitive > Start INTiIC register: bits ILVL2 to ILVL0 = 000b IFSR register: IFSRi bit INTiIC register: POL bit LVS bit = 0 INTiIC register: IR bit = 0 INTiIC register: ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Start IIOjIE register: INTiE bit = 0 IFSRA register: IFSRk bit IIOjIR register: INTiR bit = 0 IIOjIE register: INTiE bit = 1 End Figure 11.12 INTi Interrupt Setting Procedures ( ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) External Interrupt Source Select Register1 Symbol IFSRA Bit Symbol IFSR10 IFSR11 IFSR12 − (b7-b3) NOTE: 1. The IFSRA register is available in ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 11.8 NMI Interrupt The NMI interrupt is non-maskable. The NMI interrupt occurs when a signal applied to the P8_5/NMI pin changes from “H” level to “L” level. A read from the P8_5 bit in the ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 11.10 Address Match Interrupt The address match interrupt is non-maskable. This interrupt occurs immediately before executing the instruction stored in the address specified by the RMADi register (i=0 to 7). Eight addresses can be set ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 11.11 Intelligent I/O Interrupts, CAN Interrupts, UART5 and UART6 Transmit/ Receive Interrupts, and INT6 to INT8 Interrupts The intelligent I/O interrupts are shared by CAN interrupt, INT6 to INT8 interrupts, UART5 and UART6 transmit/ receive ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Interrupt Request Register Symbol IIO0IR to IIO11IR Bit Symbol − (b0) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) NOTES: 1. ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Interrupt Enable Register Symbol IIO0IE to IIO11E Bit Symbol IRLT (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) NOTES: 1. See ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) To configure for intelligent I/O interrupts, use IIOiIE register ( 11), IIOiIR register, and IIOiIC (CANjIC ( 5)) register. 11.11.1 IIOiIE Register • IRLT bit Set ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) “H” Interrupt request A from peripheral function A “L” “H” Interrupt request B from peripheral function B “L” Interrupt request flag (1) 1 corresponding to interrupt request A 0 Interrupt request flag (1) 1 corresponding ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Example: Intelligent I/O Group 1 Waveform Generation Function 1 Interrupt, Group 2 Waveform Generation Function 3 Interrupt are used. <Interrupt setting> IIO8IR register = 00h IIO8IE register: IRLT bit = 1 IIO8IE register: PO11E bit ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 12. Watchdog Timer The watchdog timer is used to detect the program running improperly. The watchdog timer contains a 15-bit free- running counter write to the WDTS register is not performed due to ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Prescaler 1/16 CPU clock 1/128 Wait mode signal HOLD 1/2 On-chip oscillator clock Write signal to the WDTS register Internal reset signal CM06, CM07: bits in the CM0 register WDC7: bit in the WDC register ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) System Clock Control Register Symbol CM0 Bit Symbol CM00 CM01 CM02 CM03 CM04 CM05 CM06 CM07 NOTES: 1. Set the CM0 register after the PRC0 bit ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Watchdog Timer Control Register Symbol 0 WDC Bit Symbol − (b4-b0) WDC5 − (b6) WDC7 NOTES: 1. The WDC5 bit is 0 after power-on. It can be ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 13. DMAC DMAC allows data to be sent to and from memory without involving the CPU. The M32C/87 Group (M32C/87, M32C/87A, M32C/87B) has four DMAC channels. DMAC transfers 16-bit data from a ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) A software trigger or an interrupt request generated by individual peripheral functions can be the DMA transfer request source. Bits DSEL 4 to DSEL0 in the DMiSL register determine which source is selected. When a ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) DMAi Request Source Select Register (i Symbol DM0SL to DM3SL Bit Symbol DSEL0 DSEL1 DSEL2 DSEL3 DSEL4 DSR − (b6) DRQ NOTES: 1. Change settings ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 13.2 DMiSL Register ( Function Setting Value DMA0 Software trigger Falling edge of INT0 0 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) DMAi Memory Address Register ( Symbol b23 b16 b15 DMA0 DMA1 DMA2 (bank1:A0) DMA3 (bank1:A1) Set an incremented source address or incremented destination address NOTES: 1. When the ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) DMAi Memory Address Reload Register Symbol b23 b16 b15 DRA0 DRA1 DRA2 (SVP) DRA3 (VCT) Set an incremented source address or incremented destination address NOTES: 1. Use the LDC instruction to set ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) DMA Mode Register Symbol DMD0 Bit Symbol MD00 MD01 BW0 RW0 MD10 MD11 BW1 RW1 NOTE: 1. Use the LDC instruction to set the DMD0 register. ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) DMA Mode Register 1 Symbol DMD1 Bit Symbol MD20 MD21 BW2 RW2 MD30 MD31 BW3 RW3 NOTE: 1. Use the LDC instruction to set the DMD1 register. ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Start Set the peripheral function used as DMAi request source DMD0 register: bits MD01 and MD00 = 00b bits MD11 and MD10 = 00b DMiSL register: bits DSEL4 to DSEL0 DSR bit = 0 DRQ ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Start Set the peripheral function used as DMAi request source DMD1 register: bits MD21 and MD20 = 00b bits MD31 and MD30 = 00b DMiSL register: bits DSEL4 to DSEL0 DSR bit = 0 DRQ ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 13.1 Transfer Cycles The transfer cycle is composed of bus cycles to read data from source address (source read) and bus cycles to write data to destination address (destination write). The number of read and ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 13.2 DMA Transfer Time The DMA transfer time can be calculated as follows. (in terms of bus clock) Table 13.3 lists the number of the source read cycle and destination write cycle. Table 13.4 lists ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Example when DMA transfer requests for DMA0 and DMA1 are generated simultaneously and DMA transfers (SFR to RAM) are performed in minimum time. BCLK DMA0 DMA1 CPU INT0 DRQ bit in DMA0 INT1 DRQ bit ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 14. DMACII DMACII performs memory-to-memory transfer, immediate data transfer, and calculation transfer which transfers a result of the addition of two data. DMACII transfer occurs in response to interrupt requests from the peripheral functions. Table ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Exit Priority Register Symbol RLVL Bit Symbol RLVL0 RLVL1 RLVL2 FSIT − (b4) DMAII − (b7-b6) NOTES: 1. The MCU exits stop or wait mode when an ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 14.1.2 DMACII Index The DMACII index 32-byte data table, which stores parameters for transfer mode, transfer counter, source address (or immediate data), operation address as an address to be calculated, destination ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 14.2 DMACII Index Configuration in Transfer Mode Memory-to-Memory Transfer/ Transfer data Immediate Data Transfer Chain transfer Not used Used End-of- Transfer Not used Not used Interrupt DMAC II index MOD MOD COUNT COUNT SADR ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 14.1.3 Interrupt Control Register for the Peripheral Function To use the peripheral function interrupt as a DMACII request source, set bits ILVL2 to ILVL0 to 111b (level 7). 14.1.4 Relocatable Vector Table for the Peripheral ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 14.3.2 Immediate Data Transfer DMACII transfers immediate data to a given memory location. A fixed or incremented address can be selected as a destination address. Store immediate data into SADR. To transfer an 8-bit immediate ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 14.5 Chain Transfer The chain transfer can be selected with the CHAIN bit in MOD. The chain transfer is performed as follows. (1) Transfer occurs in response to an interrupt request from a peripheral function ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 14.7 Execution Time DMACII execution time is calculated by the following equations (single-speed mode): Multiple transfers: t [bus clock] = 21+ ( × k Other than multiple transfers: t [bus clock] ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 15. Timers The M32C/87 Group (M32C/87, M32C/87A, M32C/87B) has eleven 16-bit timers, and they are separated into five timer A and six timer B based on their functions. Individual timers function independently. The count source ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) XCIN Timer B2 overflow or underflow signal f1 f8 f2n fC32 (to the count source of timer A) TCK1 and TCK0 Noise TB0IN filter TCK1 and TCK0 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 15.1 Timer A Timer A contains the following four modes. Except in event counter mode, all timers have the same functionality. Bits TMOD1 and TMOD0 in the TAiMR register ( ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Count Source Prescaler Register Symbol TCSPR Bit Symbol CNT0 CNT1 CNT2 CNT3 − (b6-b4) CST NOTES: 1. Set the CST bit to 0 before bits CNT3 to ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Timer Ai Mode Register ( 4)(Timer Mode) Symbol TA0MR to TA4MR Bit Symbol TMOD0 TMOD1 − (b2) MR1 MR2 MR3 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Timer Ai Mode Register ( 4)(Event Counter Mode) Symbol TA0MR to TA4MR Bit Symbol TMOD0 TMOD1 − (b2) MR1 MR2 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Timer Ai Mode Register ( 4)(One-Shot Timer Mode) Symbol TA0MR to TA4MR Bit Symbol TMOD0 TMOD1 − (b2) MR1 MR2 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Timer Ai Mode Register ( 4)(Pulse Width Modulation Mode) Symbol TA0MR to TA4MR Bit Symbol TMOD0 TMOD1 − (b2) MR1 MR2 ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Timer Ai Register ( Symbol b0 b15 b8 b7 TA0 to TA2 TA3, TA4 Timer mode Event counter mode One-shot timer mode Pulse width modulation mode (16-bit PWM) Pulse width ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Up/Down Select Register Symbol UDF Bit Symbol TA0UD TA1UD TA2UD TA3UD TA4UD TA2P TA3P TA4P NOTES: 1. Read-modify-write instructions cannot be used to set the UDF register. ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Trigger Select Register Symbol TRGSR Bit Symbol TA1TGL TA1TGH TA2TGL TA2TGH TA3TGL TA3TGH TA4TGL TA4TGH NOTE: 1. Overflow or underflow. Figure 15.11 TRGSR Register REJ09B0180-0151 Rev.1.51 Jul ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Count Start Register Symbol TABSR Bit Symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Figure 15.12 TABSR Register REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 170 of ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) One-Shot Start Register Symbol ONSF Bit Symbol TA0OS TA1OS TA2OS TA3OS TA4OS TAZIE TA0TGL TA0TGH NOTES: 1. Read Overflow or underflow. Figure 15.13 ONSF ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 15.1 TAiOUT Pin Settings in Output Mode ( Port Function (2) P7_0 TA0OUT P7_2 TA1OUT P7_4 TA2OUT P7_6 TA3OUT P8_0 TA4OUT NOTES: 1. Set registers PS1and PS2 after setting registers ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 15.1.1 Timer Mode In timer mode, the timer counts an internally generated count source. Table 15.3 lists specifications of timer mode. Figure 15.14 shows a timer mode operation (Timer A). Table 15.3 Specifications of Timer ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 15.1.2 Event Counter Mode In event counter mode, the timer counts overflows/underflows of another timer, or the external pulse input. Timers A2, A3, and A4 can count externally generated two-phase signals. Table 15.4 lists specifications ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) FFFFh n Contents of the counter n = contents of the reload register 0000h “H” Input to TAiIN pin “L” 1 TAiS bit in the TABSR register 0 1 TAiUD bit in the UDF register ...
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 15.5 Specifications of Event Counter Mode When Handling Two-Phase Pulse Signals on Timers A2, A3, and A4 Item Count source Count operation Number of counting Count start condition Count stop condition Interrupt request generation ...