M30879FLFP#U3 Renesas Electronics America, M30879FLFP#U3 Datasheet - Page 181
![IC M32C/87 MCU FLASH 100QFP](/photos/12/31/123127/m30879flfp_u3_sml.jpg)
M30879FLFP#U3
Manufacturer Part Number
M30879FLFP#U3
Description
IC M32C/87 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(93 pages)
2.M3087BFLGPU3.pdf
(629 pages)
3.M3087BFLGPU3.pdf
(364 pages)
Specifications of M30879FLFP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Manufacturer
Quantity
Price
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 157 of 587
14.5
Figure 14.4
14.6
The chain transfer can be selected with the CHAIN bit in MOD.
The chain transfer is performed as follows.
Figure 14.4 shows the relocatable vector and DMACII index when using the chain transfer.
For the chain transfer, the relocatable vector table must be located in the RAM.
The end-of-transfer interrupt can be selected with the INTE bit in MOD. Set the starting address of the end-of-
transfer interrupt routine in IADR1 and IADR0. The end-of-transfer interrupt occurs when COUNT reaches zero.
(1) Transfer occurs in response to an interrupt request from a peripheral function and is performed according to
(2) When COUNT reaches zero, the interrupt vector in (1) is replaced with the address written in CADR1 and
(3) When the next DMACII transfer request is generated, the transfer is performed according to the contents of
Chain Transfer
End-of-Transfer Interrupt
the contents of the DMACII index at the address specified by the interrupt vector. For one transfer request,
either a single transfer or burst transfer selected by the BRST bit in MOD occurs.
CADR0. The end-of-transfer interrupt occurs after the replacement, if the INTE bit in MOD is set to 1.
the DMACII index specified by the interrupt vector which has been replaced in (2).
Relocatable
Vector
DMACII index (a)
DMACII index (b)
Relocatable Vector and DMACII Index When using the Chain Transfer
INTB
BASE (a)
(CADR1,
CADR0)
BASE (b)
(CADR1,
CADR0)
BASE (b)
BASE (c)
RAM
Interrupt vector of the peripheral function triggering
DMACII request. Default value is BASE (a).
When COUNT reaches zero, the interrupt vector
is replaced wtih BASE (c).
When the next request occurs, a transfer starts
according to the contents of the DMACII index at
BASE (b).
When COUNT reaches zero, the above interrupt
vector is replaced with BASE (b), which is the
address written in CADR1 and CADR0.
14. DMACII
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