M30879FLFP#U3 Renesas Electronics America, M30879FLFP#U3 Datasheet - Page 319
M30879FLFP#U3
Manufacturer Part Number
M30879FLFP#U3
Description
IC M32C/87 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(93 pages)
2.M3087BFLGPU3.pdf
(629 pages)
3.M3087BFLGPU3.pdf
(364 pages)
Specifications of M30879FLFP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 295 of 587
Figure 18.2
A/D0 Control Register 0
b7 b6 b5 b4
NOTES:
1. If the AD0CON0 register is rewritten during A/D conversion, the conversion result will be incorrect.
2. Analog input pins must be configured again after an A/D operating mode is changed.
3. Bits CH2 to CH0 are enabled in one-shot mode and repeat mode.
4. To set the TRG bit to 1, select a trigger source using the TRG0 bit in the AD0CON2 register. Then, set the ADST bit to 1 after
5. φ AD frequency must be 16 MHz or lower when VCC1 = 4.2 to 5.5V.
the TRG bit is set to 1.
φ AD frequency must be 10 MHz or lower when VCC1 = 3.0 to 5.5V.
φ AD is selected by the combination of the CKS0 bit, the CKS1 in the AD0CON1 register, and the CKS2 bit in the AD0CON3
register.
b3
in AD0CON3 register
b2
AD0CON0 Register
b1
CKS2 bit
b0
0
1
Bit Symbol
ADST
CKS0
MD0
MD1
TRG
CH0
CH1
CH2
Symbol
AD0CON0
in AD0CON0 register
(1)
Analog input pin
select bits
A/D operating mode
select bits 0
Trigger select bit
A/D conversion start bit
Frequency select bit 0
CKS0 bit
0
1
0
(2, 3)
Bit Name
(2)
in AD0CON1 register
Address
0396h
CKS1 bit
0
1
0
1
0
1
b2 b1 b0
0 0 0: ANi_0
0 0 1: ANi_1
0 1 0: ANi_2
0 1 1: ANi_3
1 0 0: ANi_4
1 0 1: ANi_5
1 1 0: ANi_6
1 1 1: ANi_7 (i = none, 0, 2, 15)
When the MSS bit in the AD0CON3 register = 0
b4 b3
0 0: One-shot mode
0 1: Repeat mode
1 0: Single sweep mode
1 1: Repeat sweep mode 0, repeat sweep mode 1
When the MSS bit in the AD0CON3 register = 1
b4 b3
0 0:
0 1:
1 0: Multi-port single sweep mode
1 1: Multi-port repeat sweep mode 0
0: Software trigger
1: External trigger, hardware trigger
0: A/D conversion stops
1: A/D conversion starts
(Note 5)
Do not set to these values.
fAD divided by 4
fAD divided by 3
fAD divided by 2
fAD divided by 8
fAD divided by 6
Function
φ AD
fAD
(4)
(4)
After Reset
00h
18. A/D Converter
RW
RW
RW
RW
RW
RW
RW
RW
RW
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