MCIMX515CJM6C Freescale Semiconductor, MCIMX515CJM6C Datasheet - Page 13

MULTIMEDIA PROC 529-LFBGA

MCIMX515CJM6C

Manufacturer Part Number
MCIMX515CJM6C
Description
MULTIMEDIA PROC 529-LFBGA
Manufacturer
Freescale Semiconductor
Series
i.MX51r
Datasheets

Specifications of MCIMX515CJM6C

Core Processor
ARM Cortex-A8
Core Size
32-Bit
Speed
600MHz
Connectivity
1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
128
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.8 V ~ 1.15 V
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
529-LFBGA
Processor Series
i.MX51
Core
ARM Cortex A8
Data Bus Width
32 bit
Program Memory Size
36 KB
Data Ram Size
128 KB
Interface Type
I2C, SPI, SSI, UART, USB
Maximum Clock Frequency
200 MHz
Number Of Timers
5
Operating Supply Voltage
0.8 V to 1.15 V
Maximum Operating Temperature
+ 95 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
MCIMX51EVKJ
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCIMX515CJM6C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCIMX515CJM6C
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MCIMX515CJM6CR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor
PMIC_INT_REQ
POR_B
RESET_IN_B
RREFEXT
SGND, SVCC, and
SVDDGP
STR
TEST_MODE
VREF
VREFOUT
Signal Name
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
When using the MC13892 power management IC, the PMIC_INT_REQ high-priority interrupt input
on i.MX51 should be either floated or tied to NVCC_SRTC_POW with a 4.7 kΩ to 68 kΩ resistor.
This avoids a continuous current drain on the real-time clock backup battery due to a 100 kΩ
on-chip pull-up resistor.
PMIC_INT_REQ is not used by the Freescale BSP (board support package) software. The BSP
requires that the general-purpose INT output from the MC13892 be connected to the i.MX51 GPIO
input GPIO1_8 configured to cause an interrupt that is not high-priority.
The original intent was for PMIC_INT_REQ to be connected to a circuit that detects when the
battery is almost depleted. In this case, the I/O must be configured as alternate mode 0 (ALT0 =
power fail).
This cold reset negative logic input resets all modules and logic in the IC.
Note: The POR_B input must be immediately asserted at power-up and remain asserted until
after the last power rail is at its working voltage.
This warm reset negative logic input resets all modules and logic except for the following:
Determines the reference current for the USB PHY bandgap reference. An external 6.04 kΩ 1%
resistor to GND is required.
These sense lines provide the ability to sense actual on-chip voltage levels on their respective
supplies. SGND monitors differentials of the on-chip ground versus an external power source.
SVCC monitors on-chip VCC, and SVDDGP monitors VDDGP. Freescale recommends
connection of the SVCC and SVDDGP signals to the feedback inputs of switching power-supplies
or to test points.
This signal is reserved for Freescale manufacturing use. The user should float this signal.
TEST_MODE is for Freescale factory use only. This signal is internally connected to an on-chip
pull-down device. Users must either float this signal or tie it to GND.
When using VREF with DDR-2 I/O, the nominal 0.9 V reference voltage must be half of the
NVCC_EMI_DRAM supply. The user must tie VREF to a precision external resistor divider. Use a
1 kΩ 0.5% resistor to GND and a 1 kΩ 0.5% resistor to NVCC_EMI_DRAM. Shunt each resistor
with a closely-mounted 0.1 µF capacitor.
To reduce supply current, a pair of 1.5 kΩ 0.1% resistors can be used. Using resistors with
recommended tolerances ensures the ± 2% VREF tolerance (per the DDR-2 specification) is
maintained when four DDR-2 ICs plus the i.MX51 are drawing current on the resistor divider.
Note: When VREF is used with mDDR this signal must be tied to GND.
This signal determines the Triple Video DAC (TVDAC) reference voltage. The user must tie
VREFOUT to an external 1.05 kΩ 1% resistor to GND.
• Test logic (JTAG, IOMUXC, DAP)
• SRTC
• Memory repair – Configuration of memory repair per fuse settings
• Cold reset logic of WDOG – Some WDOG logic is only reset by POR_B. See WDOG chapter
in i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM) for details.
Table 3. Special Signal Considerations (continued)
Remarks
Features
13

Related parts for MCIMX515CJM6C