ATTINY40-MMHR Atmel, ATTINY40-MMHR Datasheet - Page 118

• Manufacturer Part Number: ATTINY40-MMHR
• Description: MCU AVR 4KB FLASH 12MHZ 3X3 QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY40-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.13.2
15.13.2.1
15.13.2.2
118
ATtiny40
ADCL and ADCH – ADC Data Register
ADLAR = 0
ADLAR = 1
Table 15-4.
Notes:
If these bits are changed during a conversion, the change will not go into effect until this
conversion is complete (ADIF in ADCSRA is set).
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADCSRB, and the MUX bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC[9:0]: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
Bit
0x0F
0x0E
Read/Write
Initial Value
Bit
0x0F
0x0E
Read/Write
Initial Value
Single Ended Input
ADC10 (PB2)
ADC11 (PB3)
0V (AGND)
1.1V (I Ref)
ADC12 (Temperature Sensor)
Reserved
116.
1. See
Single-Ended Input channel Selections (Continued)
“Temperature Measurement” on page
ADC7
ADC9
ADC1
15
15
R
R
R
R
–
7
0
0
7
0
0
ADC6
ADC8
ADC0
14
14
R
R
R
R
–
6
0
0
6
0
0
(1)
ADC5
ADC7
13
13
R
R
R
R
–
5
0
0
–
5
0
0
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
–
4
0
0
116.
ADC3
ADC5
11
11
R
R
R
R
–
3
0
0
–
3
0
0
ADC2
ADC4
10
10
R
R
R
R
–
2
0
0
–
2
0
0
“ADC Conversion Result” on
ADC9
ADC1
ADC3
R
R
R
R
9
1
0
0
9
–
1
0
0
MUX[3:0]
1010
1011
1100
1101
1110
1111
ADC8
ADC0
ADC2
8
0
R
R
0
0
8
–
0
R
R
0
0
8263A–AVR–08/10
ADCH
ADCH
ADCL
ADCL