ATTINY40-MMHR Atmel, ATTINY40-MMHR Datasheet - Page 86

• Manufacturer Part Number: ATTINY40-MMHR
• Description: MCU AVR 4KB FLASH 12MHZ 3X3 QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY40-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.5.1
12.5.2
12.5.3
86
ATtiny40
Input Capture Trigger Source
Noise Canceler
Using the Input Capture Unit
OCR1B serves as the high byte of the Input Capture Register ICR1. In 8-bit Input Capture mode
the Output Compare Register OCR1B is free to be used as a normal Output Compare Register,
but in 16-bit Input Capture mode the Output Compare Unit cannot be used as there are no free
Output Compare Register(s). Even though the Input Capture register is called ICR1 in this sec-
tion, it is refering to the Output Compare Register(s).
When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), and this
change confirms to the setting of the edge detector, a capture will be triggered. When a capture
is triggered, the value of the counter (TCNT1) is written to the Input Capture Register (ICR1).
The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied into
Input Capture Register. If enabled (ICIE1=1), the Input Capture Flag generates an Input Capture
interrupt. The ICF1 flag is automatically cleared when the interrupt is executed. Alternatively the
ICF1 flag can be cleared by software by writing a logical one to its I/O bit location.
The trigger source for the Input Capture unit is the Input Capture pin (ICP1).
The Input Capture pin (ICP1) input is sampled using the same technique as for the T1 pin
ure 12-4 on page
enabled, additional logic is inserted before the edge detector, which increases the delay by four
system clock cycles. An Input Capture can also be triggered by software by controlling the port
of the ICP1 pin.
The noise canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monitored over four samples, and all four must be equal for changing the
output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in
Timer/Counter Control Register A (TCCR1A). When enabled the noise canceler introduces addi-
tional four system clock cycles of delay from a change applied to the input, to the update of the
ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the
prescaler.
The main challenge when using the Input Capture unit is to assign enough processor capacity
for handling the incoming events. The time between two events is critical. If the processor has
not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be
overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICR1 Register should be read as early in the inter-
rupt handler routine as possible. The maximum interrupt response time is dependent on the
maximum number of clock cycles it takes to handle any of the other interrupt requests.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after
each capture. Changing the edge sensing must be done as early as possible after the ICR1
Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be
cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,
the trigger edge change is not required (if an interrupt handler is used).
94). The edge detector is also identical. However, when the noise canceler is
8263A–AVR–08/10
(Fig-