ATTINY40-MMHR Atmel, ATTINY40-MMHR Datasheet - Page 120

• Manufacturer Part Number: ATTINY40-MMHR
• Description: MCU AVR 4KB FLASH 12MHZ 3X3 QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY40-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.13.4
120
ATtiny40
ADCSRB – ADC Control and Status Register B
Table 15-5.
• Bit 7 – VDEN
This bit is reserved for QTouch, always write as zero.
• Bit 6 – VDPD
This bit is reserved for QTouch, always write as zero.
• Bits 5:4 – Res: Reserved Bits
These are reserved bits. For compatibility with future devices always write these bits to zero.
• Bit 3 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a comple the description of this bit, see
page
• Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conver-
sion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a
trigger source that is cleared to a trigger source that is set, will generate a positive edge on the
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set
Table 15-6.
Bit
0x11
Read/Write
Initial Value
118.
ADTS2
ADPS2
0
0
0
0
1
1
1
1
ADC Prescaler Selections (Continued)
ADC Auto Trigger Source Selections
VDEN
R/W
7
0
ADTS1
VDPD
R/W
ADPS1
6
0
0
0
1
1
0
0
1
1
R
5
–
0
ADTS0
R
4
–
0
ADPS0
0
1
0
1
0
1
0
1
“ADCL and ADCH – ADC Data Register” on
ADLAR
R/W
3
0
Trigger Source
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter0 Compare Match A
Timer/Counter0 Overflow
ADTS2
R/W
2
0
ADTS1
Division Factor
R/W
1
0
128
32
64
ADTS0
R/W
0
0
8263A–AVR–08/10
.
ADCSRB