ATTINY40-MMHR Atmel, ATTINY40-MMHR Datasheet - Page 20

• Manufacturer Part Number: ATTINY40-MMHR
• Description: MCU AVR 4KB FLASH 12MHZ 3X3 QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY40-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6. Clock System
6.1
6.1.1
6.1.2
6.1.3
20
Clock Subsystems
ATtiny40
CPU Clock – clk
I/O Clock – clk
NVM clock - clk
I/O
Figure 6-1
clocks need not be active at a given time. In order to reduce power consumption, the clocks to
modules not being used can be halted by using different sleep modes and power reduction reg-
ister bits, as described in
systems is detailed below.
Figure 6-1.
The clock subsystems are detailed in the sections below.
The CPU clock is routed to parts of the system concerned with operation of the AVR Core.
Examples of such modules are the General Purpose Register File, the System Registers and
the SRAM data memory. Halting the CPU clock inhibits the core from performing general opera-
tions and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is
also used by the External Interrupt module, but note that some external interrupts are detected
by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.
The NVM clock controls operation of the Non-Volatile Memory Controller. The NVM clock is usu-
ally active simultaneously with the CPU clock.
NVM
CPU
presents the principal clock systems and their distribution in ATtiny40. All of the
ANALOG-TO-DIGITAL
Clock Distribution
PRESCALER
CONVERTER
SWITCH
CLOCK
CLOCK
EXTERNAL
CLOCK
SOURCE CLOCK
clk
ADC
“Power Management and Sleep Modes” on page
CLOCK CONTROL UNIT
I/O MODULES
GENERAL
OSCILLATOR
clk
WATCHDOG
RESET
I/O
LOGIC
WATCHDOG
CLOCK
CORE
CPU
clk
RAM
CPU
WATCHDOG
TIMER
CALIBRATED
OSCILLATOR
clk
NVM
NVM
27. The clock
8263A–AVR–08/10