ATTINY2313A-SUR Atmel, ATTINY2313A-SUR Datasheet - Page 115

• Manufacturer Part Number: ATTINY2313A-SUR
• Description: MCU AVR 2KB FLASH 20MHZ 20SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313A-SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

12.11.8
12.11.9
8246A–AVR–11/09
TIMSK – Timer/Counter Interrupt Mask Register
TIFR – Timer/Counter Interrupt Flag Register
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 7 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page
• Bit 6 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector
TIFR, is set.
• Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector
TIFR, is set.
• Bit 3 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector
• Bit 7 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes,
the TOV1 flag is set when the timer overflows. Refer to
flag behavior when using another WGM13:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.
Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
Bit
0x39 (0x59)
Read/Write
Initial Value
Bit
0x38 (0x58)
Read/Write
Initial Value
(See “Interrupts” on page
See “Accessing 16-bit Registers” on page 106.
TOIE1
TOV1
R/W
R/W
7
0
7
0
(See “Interrupts” on page
(See “Interrupts” on page
OCIE1A
OCF1A
R/W
R/W
6
0
6
0
47.) is executed when the TOV1 flag, located in TIFR, is set.
OCIE1B
OCF1B
R/W
R/W
5
0
5
0
47.) is executed when the ICF1 flag, located in TIFR, is set.
R
4
–
0
R
4
–
0
47.) is executed when the OCF1A flag, located in
47.) is executed when the OCF1B flag, located in
ICF1
ICIE1
R/W
R/W
3
0
3
0
OCF0B
OCIE0B
R/W
R/W
2
0
Table 12-5 on page 112
2
0
TOV0
TOIE0
R/W
R/W
1
0
1
0
OCF0A
OCIE0A
R/W
R/W
0
0
0
0
TIMSK
TIFR
for the TOV1
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