ATTINY2313A-SUR Atmel, ATTINY2313A-SUR Datasheet - Page 88

• Manufacturer Part Number: ATTINY2313A-SUR
• Description: MCU AVR 2KB FLASH 20MHZ 20SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313A-SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

12. 16-bit Timer/Counter1
12.1
12.2
88
Features
Overview
ATtiny2313A/4313
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The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement.
A simplified block diagram of the 16-bit Timer/Counter is shown in
placement of I/O pins, refer to
ters, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit
locations are listed in the
Figure 12-1. 16-bit Timer/Counter Block Diagram
Note:
True 16-bit Design (i.e., Allows 16-bit PWM)
Two independent Output Compare Units
Double Buffered Output Compare Registers
One Input Capture Unit
Input Capture Noise Canceler
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
External Event Counter
Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
Refer to
Figure 1-1 on page 2
Timer/Counter
TCCRnA
“Register Description” on page
OCRnA
OCRnB
TCNTn
ICRn
=
=
“Pinout ATtiny2313A/4313” on page
Direction
for Timer/Counter1 pin placement and description.
Count
Clear
Control Logic
TOP
=
TCCRnB
Values
BOTTOM
Fixed
TOP
ICFn (Int.Req.)
(Note:)
clk
Detector
Edge
=
Tn
0
110.
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TOVn
(Int.Req.)
Clock Select
Generation
Generation
Waveform
Waveform
( From Prescaler )
Canceler
Detector
Noise
Edge
2. CPU accessible I/O Regis-
Figure
Comparator Ouput )
( From Analog
12-1. For the actual
OCnA
OCnB
ICPn
Tn
8246A–AVR–11/09