ATTINY2313A-SUR Atmel, ATTINY2313A-SUR Datasheet - Page 48

• Manufacturer Part Number: ATTINY2313A-SUR
• Description: MCU AVR 2KB FLASH 20MHZ 20SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313A-SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

9.2
48
External Interrupts
ATtiny2313A/4313
The most typical and general setup for the Interrupt Vector Addresses in ATtiny2313A/4313
shown below:
External Interrupts are triggered by the INT0 or INT1 pin or any of the PCINT17..0 pins. Observe
that, if enabled, the interrupts will trigger even if the INT0, INT1 or PCINT17..0 pins are config-
ured as outputs. This feature provides a way of generating a software interrupt. Pin change 0
interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles. Pin change 1 interrupts PCI1
will trigger if any enabled PCINT10..8 pin toggles. Pin change 2 interrupts PCI2 will trigger, if any
enabled PCINT17..11 pin toggles. The PCMSK0, PCMSK1, and PCMSK2 Registers control
which pins contribute to the pin change interrupts. Pin change interrupts on PCINT17..0 are
detected asynchronously, which means that these interrupts can be used for waking the part
also from sleep modes other than Idle mode.
The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is
set up as shown in
rupt is enabled and configured as level triggered, the interrupt will trigger as long as the pin is
held low. Note that recognition of falling or rising edge interrupts on INT0 or INT1 requires the
presence of an I/O clock, as described in
Address Labels Code
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000C
0x000D
0x000E
0x000F
0x0010
0x0011
0x0012
0x0013
0x0014
;
0x0013
0x0014
0x0015
0x0016
...
RESET: ldi
...
“MCUCR – MCU Control Register” on page
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
rjmp
out
sei
<instr>
...
...
RESET
INT0
INT1
TIM1_CAPT
TIM1_COMPA
TIM1_OVF
TIM0_OVF
USART0_RXC
USART0_DRE
USART0_TXC
ANA_COMP
PCINT0
TIMER1_COMPB
TIMER0_COMPA
TIMER0_COMPB
USI_START
USI_OVERFLOW
EE_READY
WDT_OVERFLOW
PCINT1
PCINT2
r16, low(RAMEND); Main program start
SPL,r16
xxx
“Clock Sources” on page
Comments
; Reset Handler
; External Interrupt0 Handler
; External Interrupt1 Handler
; Timer1 Capture Handler
; Timer1 CompareA Handler
; Timer1 Overflow Handler
; Timer0 Overflow Handler
; USART0 RX Complete Handler
; USART0,UDR Empty Handler
; USART0 TX Complete Handler
; Analog Comparator Handler
; PCINT0 Handler
; Timer1 Compare B Handler
; Timer0 Compare A Handler
; Timer0 Compare B Handler
; USI Start Handler
; USI Overflow Handler
; EEPROM Ready Handler
; Watchdog Overflow Handler
; PCINT1 Handler
; PCINT2 Handler
; Enable interrupts
Set Stack Pointer to top of RAM
50. When the INT0 or INT1 inter-
25.
8246A–AVR–11/09