ATTINY48-MMH Atmel, ATTINY48-MMH Datasheet - Page 179
![MCU AVR 4KB FLASH 12MHZ 28-VQFN](/photos/12/32/123209/28m1-vqfn_sml.jpg)
ATTINY48-MMH
Manufacturer Part Number
ATTINY48-MMH
Description
MCU AVR 4KB FLASH 12MHZ 28-VQFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY48-MMH
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
For Use With
ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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17.13.3
17.13.3.1
17.13.3.2
17.13.4
8008G–AVR–04/11
ADCL and ADCH – The ADC Data Register
ADCSRB – ADC Control and Status Register B
ADLAR = 0
ADLAR = 1
Table 17-5.
• ADC[9:0]: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
page
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• Bits 7, 5:3 – Res: Reserved Bits
These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be written to zero when ADCSRB is written.
Bit
(0x79)
(0x78)
Read/Write
Initial Value
Bit
(0x79)
(0x78)
Read/Write
Initial Value
Bit
(0x7B)
Read/Write
Initial Value
ADPS2
175.
1
1
1
ADC Prescaler Selections (Continued)
ADC7
ADC9
ADC1
15
15
R
R
R
R
7
0
0
–
7
0
0
R
7
–
0
ADPS1
0
1
1
ADC6
ADC8
ADC0
ACME
R/W
14
14
R
R
R
R
6
0
0
–
6
0
0
6
0
ADC5
ADC7
ADPS0
13
13
R
R
R
R
–
5
0
0
–
5
0
0
R
5
–
0
1
0
1
ADC4
ADC6
12
12
R
R
R
R
–
4
0
0
–
4
0
0
R
4
–
0
ADC3
ADC5
11
11
R
R
R
R
–
3
0
0
–
3
0
0
R
3
–
0
ADTS2
ADC4
ADC2
R/W
10
10
R
R
–
2
R
R
0
0
–
2
0
0
2
0
Division Factor
“ADC Conversion Result” on
128
32
64
ADTS1
ADC3
ADC9
ADC1
R/W
R
R
R
R
9
–
1
0
0
9
1
0
0
1
0
ATtiny48/88
ADTS0
ADC2
ADC8
ADC0
R/W
R
R
R
R
8
–
0
0
0
8
0
0
0
0
0
ADCSRB
ADCH
ADCL
ADCH
ADCL
179
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