ATTINY48-MMH Atmel, ATTINY48-MMH Datasheet - Page 185
![MCU AVR 4KB FLASH 12MHZ 28-VQFN](/photos/12/32/123209/28m1-vqfn_sml.jpg)
ATTINY48-MMH
Manufacturer Part Number
ATTINY48-MMH
Description
MCU AVR 4KB FLASH 12MHZ 28-VQFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY48-MMH
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
For Use With
ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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19.1.1
19.1.2
8008G–AVR–04/11
EEPROM Write Prevents Writing to SPMCSR
Reading the Fuse and Lock Bits from Software
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the RFLB and SELFPRGEN bits in SPMCSR. When an LPM
instruction is executed within three CPU cycles after the RFLB and SELFPRGEN bits are set in
SPMCSR, the value of the Lock bits will be loaded in the destination register. The RFLB and
SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruc-
tion is executed within three CPU cycles or no SPM instruction is executed within four CPU
cycles. When RFLB and SELFPRGEN are cleared, LPM will work as described in the Instruction
set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the RFLB and
SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles after
the RFLB and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB)
will be loaded in the destination register as shown below.See
detailed description and mapping of the Fuse Low byte.
Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When an LPM
instruction is executed within three cycles after the RFLB and SELFPRGEN bits are set in the
SPMCSR, the value of the Fuse High byte will be loaded in the destination register as shown
below. See
Fuse Extended byte can be read by loading the Z-pointer with 0x0002. When an LPM instruction
is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the
value of the Fuse Extended Byte (FEB) will be loaded in the destination register as shown
below. See
byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
Bit
Rd
Bit
Rd
Bit
Rd
Bit
Rd
Table 20-4 on page 189
Table 20-3 on page 189
FHB7
FLB7
FEB7
7
7
7
7
–
FHB6
FLB6
FEB6
6
6
6
6
–
FHB5
FEB5
FLB5
5
5
5
5
–
for detailed description and mapping of the Fuse High byte.
for detailed description and mapping of the Fuse Extended
FHB4
FEB4
FLB4
4
–
4
4
4
FHB3
FLB3
FEB3
3
–
3
3
3
FHB2
FEB2
FLB2
2
–
2
2
2
Table 20-5 on page 190
FHB1
FLB1
FEB1
LB2
1
1
1
1
ATtiny48/88
FHB0
FLB0
FEB0
LB1
0
0
0
0
for a
185
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