PIC16F72-I/SOG Microchip Technology, PIC16F72-I/SOG Datasheet - Page 105

• Manufacturer Part Number: PIC16F72-I/SOG
• Description: IC PIC MCU FLASH 2KX14 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F72-I/SOG

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TABLE 14-8:
© 2007 Microchip Technology Inc.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
Param
100*
101*
102*
103*
106*
107*
109*
110*
No.
90*
91*
92*
*
2: A Fast mode (400 kHz) I
These parameters are characterized but not tested.
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
requirement T
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line T
Standard mode I
T
T
T
T
T
T
T
T
T
T
T
C
Symbol
SU
SU
SU
AA
HIGH
LOW
R
F
HD
HD
BUF
B
:
:
:
:
:
STA
DAT
STO
STA
DAT
I
2
C BUS DATA REQUIREMENTS
Clock High Time
Clock Low Time
SDA and SCL Rise
Time
SDA and SCL Fall
Time
START Condition
Setup Time
START Condition
Hold Time
Data Input Hold
Time
Data Input Setup
Time
STOP Condition
Setup Time
Output Valid from
Clock
Bus Free Time
Bus Capacitive Loading
SU
:
2
DAT
C bus specification), before the SCL line is released.
≥ 250 ns must then be met. This will automatically be the case if the device does not
Characteristic
2
C bus device can be used in a Standard mode (100 kHz) I
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
R
max.+T
20 + 0.1 C
20 + 0.1 C
1.5 T
1.5 T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
SU
CY
CY
:
DAT
B
B
1000
3500
= 1000 + 250 = 1250 ns (according to the
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
μs
μs
μs
μs
ns
ns
ns
ns
μs
μs
μs
μs
ns
μs
ns
ns
μs
μs
ns
ns
μs
μs
pF
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
C
10 - 400 pF
C
10 - 400 pF
Only relevant for
Repeated START
condition
After this period, the first
clock pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
B
B
PIC16F72
2
is specified to be from
is specified to be from
C bus system, but the
Conditions
DS39597C-page 103