PIC16F72-I/SOG Microchip Technology, PIC16F72-I/SOG Datasheet - Page 48

• Manufacturer Part Number: PIC16F72-I/SOG
• Description: IC PIC MCU FLASH 2KX14 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F72-I/SOG

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PIC16F72
FIGURE 9-1:
TABLE 9-1:
DS39597C-page 46
0Bh,8Bh
10Bh,18Bh
0Ch
8Ch
87h
13h
14h
85h
94h
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.
Address
RC4/SDI/SDA
RA5/AN4/SS
RC3/SCK/
SCL
RC5/SDO
INTCON
PIR1
PIE1
TRISC
SSPBUF
SSPCON
TRISA
SSPSTAT
Name
Read
SS Control
REGISTERS ASSOCIATED WITH SPI OPERATION
Select
TRISC<3>
Edge
Enable
SSPM3:SSPM0
bit0
Select
Edge
SSP BLOCK DIAGRAM
(SPI MODE)
SSPBUF reg
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN
Bit 7
GIE
SSPSR reg
—
—
—
—
Clock Select
4
PEIE
ADIF
ADIE
Bit 6
2
—
—
Prescaler
4, 16, 64
Write
TMR2 Output
PORTA Data Direction Register
Clock
TMR0IE
Shift
Bit 5
Data Bus
D/A
Internal
—
—
2
T
CY
Bit 4
INTE
CKP
—
—
P
SSPM3 SSPM2
SSPIF
SSPIE
RBIE
Bit 3
S
To enable the serial port, SSP enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
ister, and then set bit SSPEN. This configures the SDI,
SDO, SCK, and SS pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register)
appropriately programmed. That is:
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set and ADCON must
.
cleared
be configured such that RA5 is a digital I/O
Note 1: When the SPI is in Slave mode with SS pin
TMR0IF
CCP1IF TMR2IF TMR1IF -0-- 0000 0000 0000
CCP1IE TMR2IE TMR1IE -0-- 0000 0000 0000
Bit 2
R/W
2: If the SPI is used in Slave mode with
control enabled (SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is
set to V
CKE = ‘1’, then the SS pin control must be
enabled.
SSPM1
INTF
Bit 1
UA
DD
SSPM0 0000 0000 0000 0000
.
RBIF
Bit 0
BF
© 2007 Microchip Technology Inc.
0000 000x 0000 000u
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
--00 0000 --00 0000
POR, BOR
Value on
Value on
all other
RESETS