ATTINY25V-15ST Atmel, ATTINY25V-15ST Datasheet - Page 21
ATTINY25V-15ST
Manufacturer Part Number
ATTINY25V-15ST
Description
MCU AVR 2K FLASH 4MHZ 8-SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY25-15MZ.pdf
(196 pages)
Specifications of ATTINY25V-15ST
Package / Case
8-SOIC (3.9mm Width)
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Speed
8MHz
Number Of I /o
6
Eeprom Size
128 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
128 x 8
Program Memory Size
2KB (2K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY25V-15ST
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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5.4
6. System Clock and Clock Options
6.1
7598H–AVR–07/09
I/O Memory
Clock Systems and their Distribution
The I/O space definition of the ATtiny25/45/85 is shown in
All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32
general purpose working registers and the I/O space. I/O Registers within the address range
0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the
instruction set section for more details. When using the I/O specific commands IN and OUT, the
I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using
LD and ST instructions, 0x20 must be added to these addresses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers contain-
ing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and Peripherals Control Registers are explained in later sections.
Figure 6-1
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in
ment and Sleep Modes” on page
Figure 6-1.
presents the principal clock systems in the AVR and their distribution. All of the clocks
Clock Distribution
ADC
External Clock
clk
clk
ADC
I/O
Source clock
System Clock
Control Unit
AVR Clock
Multiplexer
General I/O
Prescaler
Modules
Clock
Calibrated RC
Oscillator
Oscillator
Crystal
31. The clock systems are detailed below.
Reset Logic
clk
clk
Watchdog clock
clk
PCK
CPU
FLASH
Crystal Oscillator
Low-Frequency
CPU Core
Watchdog Timer
Watchdog
Oscillator
“Register Summary” on page
RAM
Oscillator
PLL
ATtiny25/45/85
Flash and
EEPROM
Calibrated RC
Oscillator
“Power Manage-
182.
21
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