ATMEGA32U2-AUR Atmel, ATMEGA32U2-AUR Datasheet - Page 11
![MCU AVR 32K FLASH 16MHZ 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA32U2-AUR
Manufacturer Part Number
ATMEGA32U2-AUR
Description
MCU AVR 32K FLASH 16MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U2-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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6.6
7799D–AVR–11/10
Stack Pointer
Figure 6-3.
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. Note that the Stack is implemented as
growing from higher to lower memory locations. The Stack Pointer Register always points to the
top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine
and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer.
The Stack in the data SRAM must be defined by the program before any subroutine calls are
executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the
internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see
7-2 on page
See
Table 6-1.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
X-register
Y-register
Z-register
Instruction
PUSH
CALL
ICALL
RCALL
POP
RET
RETI
Table 6-1
18.
The X-, Y-, and Z-registers
Stack Pointer instructions
Stack pointer
Decremented by 1
Decremented by 2
Incremented by 1
Incremented by 2
for Stack Pointer details.
15
7
R27 (0x1B)
15
7
R29 (0x1D)
15
7
R31 (0x1F)
Description
Data is pushed onto the stack
Return address is pushed onto the stack with a subroutine call or
interrupt
Data is popped from the stack
Return address is popped from the stack with return from
subroutine or return from interrupt
YH
ZH
XH
0
ATmega8U2/16U2/32U2
0
0
7
R28 (0x1C)
7
R26 (0x1A)
7
R30 (0x1E)
YL
XL
ZL
0
Figure
11
0
0
0
0
0
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