ATMEGA32U2-AUR Atmel, ATMEGA32U2-AUR Datasheet - Page 165
![MCU AVR 32K FLASH 16MHZ 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA32U2-AUR
Manufacturer Part Number
ATMEGA32U2-AUR
Description
MCU AVR 32K FLASH 16MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U2-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
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18.9.1
18.10 Hardware Flow Control
18.10.1
7799D–AVR–11/10
Using MPCMn
Receiver Flow Control
The Multi-processor Communication mode enables several slave MCUs to receive data from a
master MCU. This is done by first decoding an address frame to find out which MCU has been
addressed. If a particular slave MCU has been addressed, it will receive the following data
frames as normal, while the other slave MCUs will ignore the received frames until another
address frame is received.
For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZn = 7). The
ninth bit (TXB8n) must be set when an address frame (TXB8n = 1) or cleared when a data frame
(TXB = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit character
frame format.
The following procedure should be used to exchange data in Multi-processor Communication
mode:
Using any of the 5- to 8-bit character frame formats is possible, but impractical since the
Receiver must change between using n and n+1 character frame formats. This makes full-
duplex operation difficult since the Transmitter and Receiver uses the same character size set-
ting. If 5- to 8-bit character frames are used, the Transmitter must be set to use two stop bit
(USBSn = 1) since the first stop bit is used for indicating the frame type.
Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The
MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be
cleared when using SBI or CBI instructions.
The hardware flow control can be enabled by software.
CTS : (Clear to Send)
RTS : (Request to Send)
The reception flow can be controlled by hardware using the RTS pin. The aim of the flow control
is to inform the external transmitter when the internal receive Fifo is full. Thus the transmitter can
1. All Slave MCUs are in Multi-processor Communication mode (MPCMn in UCSRnA is
2. The Master MCU sends an address frame, and all slaves receive and read this frame.
3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If
4. The addressed MCU will receive all data frames until a new address frame is received.
5. When the last data frame is received by the addressed MCU, the addressed MCU sets
set).
In the Slave MCUs, the RXCn Flag in UCSRnA will be set as normal.
so, it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte and
keeps the MPCMn setting.
The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames.
the MPCMn bit and waits for a new address frame from master. The process then
repeats from 2.
HOST
RXD
TXD
CTS
RTS
ATmega8U2/16U2/32U2
TXD
RXD
CTS
RTS
ATmega8U2/16U
165
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