ATMEGA16A-AUR Atmel, ATMEGA16A-AUR Datasheet - Page 259

• Manufacturer Part Number: ATMEGA16A-AUR
• Description: MCU AVR 16KB FLASH 16MHZ 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16A-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.8.7
25.8.8
25.8.9
8154B–AVR–07/09
Setting the Boot Loader Lock Bits by SPM
EEPROM Write Prevents Writing to SPMCR
Reading the Fuse and Lock Bits from Software
as described in
the RWW section after the programming is completed, the user software must clear the
RWWSB by writing the RWWSRE. See
page 260
To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCR and
execute SPM within four clock cycles after writing SPMCR. The only accessible Lock bits are the
Boot Lock bits that may prevent the Application and Boot Loader section from any software
update by the MCU.
See
Flash access.
If bits 5:2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an
SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCR.
The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to
load the Z-pointer with $0001 (same as used for reading the Lock bits). For future compatibility It
is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock bits. When pro-
gramming the Lock bits the entire Flash can be read during the operation.
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with $0001 and set the BLBSET and SPMEN bits in SPMCR. When an LPM instruction
is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCR, the
value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN bits
will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed
within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB-
SET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
The algorithm for reading the Fuse Low bits is similar to the one described above for reading the
Lock bits. To read the Fuse Low bits, load the Z-pointer with $0000 and set the BLBSET and
SPMEN bits in SPMCR. When an LPM instruction is executed within three cycles after the BLB-
SET and SPMEN bits are set in the SPMCR, the value of the Fuse Low bits (FLB) will be loaded
in the destination register as shown below. Refer to
description and mapping of the Fuse Low bits.
Similarly, when reading the Fuse High bits, load $0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR,
Bit
R0
Bit
Rd
Bit
Rd
Table 25-2
for an example.
“Interrupts” on page
FLB7
and
7
1
7
7
–
Table 25-3
FLB6
6
6
1
6
–
for how the different settings of the Boot Loader bits affect the
BLB12
BLB12
FLB5
5
5
5
44, or the interrupts must be disabled. Before addressing
“Simple Assembly Code Example for a Boot Loader” on
BLB11
BLB11
FLB4
4
4
4
BLB02
BLB02
FLB3
3
3
3
Table 26-4 on page 266
BLB01
BLB01
FLB2
2
2
2
FLB1
LB2
ATmega16A
1
1
1
1
FLB0
LB1
0
1
0
for a detailed
0
259