ATMEGA16A-AUR Atmel, ATMEGA16A-AUR Datasheet - Page 276

• Manufacturer Part Number: ATMEGA16A-AUR
• Description: MCU AVR 16KB FLASH 16MHZ 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16A-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.8
26.8.1
276
Serial Downloading
ATmega16A
SPI Serial Programming Pin Mapping
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input), and MISO
(output). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
Table 26-11. Pin Mapping SPI Serial Programming
Figure 26-7. SPI Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the serial mode ONLY) and there is no need to first execute the Chip Erase instruc-
tion. The Chip Erase operation turns the content of every memory location in both the Program
and EEPROM arrays into $FF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the
2. V
Symbol
MOSI
MISO
SCK
XTAL1 pin.
CC
-0.3V < AVCC < V
MOSI
MISO
SCK
CC
Pins
ck
ck
PB5
PB6
PB7
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
+0.3V, however, AVCC should always be within 2.7 - 5.5V
PB5
PB6
PB7
XTAL1
RESET
GND
I/O
O
I
I
(1)
AVCC
VCC
Description
Serial Data in
Serial Data out
Serial Clock
+2.7 - 5.5V
+2.7 - 5.5V
Table 26-11 on page
ck
ck
(2)
≥ 12 MHz
≥ 12 MHz
8154B–AVR–07/09
276, the pin