AT32UC3L016-ZAUT Atmel, AT32UC3L016-ZAUT Datasheet - Page 229

• Manufacturer Part Number: AT32UC3L016-ZAUT
• Description: IC MCU AVR32 16KB FLASH 48VQFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L016-ZAUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Length: 7 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.62 V
• Width: 7 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.6.24
Name:
Access Type:
Reset Value:
There is one GCCTRL register per generic clock in the design.
• DIV: Division Factor
• OSCSEL: Oscillator Select
• DIVEN: Divide Enable
• CEN: Clock Enable
32099F–11/2010
31
23
15
7
-
-
The number of DIV bits for each generic clock is as shown in the “Generic Clock number of DIV bits” table in the SCIF Module
Configuration section.
Selects the source clock for the generic clock. Please refer to the “Generic Clock Sources” table in the SCIF Module
Configuration section.
0: The generic clock equals the undivided source clock.
1: The generic clock equals the source clock divided by 2*(DIV+1).
0: The generic clock is disabled.
1: The generic clock is enabled.
Generic Clock Control
30
22
14
6
-
-
GCCTRL
Read/Write
0x00000000
29
21
13
5
-
-
28
20
12
4
-
DIV[15:8]
DIV[7:0]
27
19
11
3
-
OSCSEL[4:0]
26
18
10
2
-
AT32UC3L016/32/64
DIVEN
25
17
9
1
CEN
24
16
8
0
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