PIC18F1330-I/SO Microchip Technology, PIC18F1330-I/SO Datasheet - Page 303

• Manufacturer Part Number: PIC18F1330-I/SO
• Description: IC PIC MCU FLASH 4KX16 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1330-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Package: 18SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

EUSART
Extended Instruction Set
External Clock Input ........................................................... 16
F
Fail-Safe Clock Monitor ............................................ 183, 197
Fast Register Stack ............................................................ 48
Firmware Instructions ....................................................... 207
Flash Program Memory ..................................................... 65
© 2007 Microchip Technology Inc.
Asynchronous Mode ................................................ 151
Baud Rate Generator
Baud Rate Generator (BRG) .................................... 145
Synchronous Master Mode ...................................... 157
Synchronous Slave Mode ........................................ 160
ADDFSR .................................................................. 250
ADDULNK ................................................................ 250
and Using MPLAB Tools .......................................... 256
CALLW ..................................................................... 251
Considerations for Use ............................................ 254
MOVSF .................................................................... 251
MOVSS .................................................................... 252
PUSHL ..................................................................... 252
SUBFSR .................................................................. 253
SUBULNK ................................................................ 253
Syntax ...................................................................... 249
Exiting Operation ..................................................... 197
Interrupts in Power-Managed Modes ....................... 198
POR or Wake From Sleep ....................................... 198
WDT During Oscillator Failure ................................. 197
Associated Registers ................................................. 73
Control Registers ....................................................... 66
Erase Sequence ........................................................ 70
Erasing ....................................................................... 70
Operation During Code-Protect ................................. 73
Reading ...................................................................... 69
Table Pointer
Table Pointer Boundaries .......................................... 68
12-Bit Break Character Sequence ................... 156
Associated Registers, Receive ........................ 154
Associated Registers, Transmit ....................... 152
Auto-Wake-up on Sync Break Character ......... 154
Receiver ........................................................... 153
Receiving a Break Character ........................... 156
Setting Up 9-Bit Mode with
Transmitter ....................................................... 151
Operation in Power-Managed Modes .............. 145
Associated Registers ....................................... 146
Auto-Baud Rate Detect .................................... 149
Baud Rate Error, Calculating ........................... 146
Baud Rates, Asynchronous Modes ................. 147
High Baud Rate Select (BRGH Bit) ................. 145
Sampling .......................................................... 145
Associated Registers, Receive ........................ 159
Associated Registers, Transmit ....................... 158
Reception ......................................................... 159
Transmission ................................................... 157
Associated Registers, Receive ........................ 161
Associated Registers, Transmit ....................... 160
Reception ......................................................... 161
Transmission ................................................... 160
EECON1 and EECON2 ..................................... 66
TABLAT (Table Latch) Register ......................... 68
TBLPTR (Table Pointer) Register ...................... 68
Boundaries Based on Operation ........................ 68
Operations with TBLRD and TBLWT (table) ...... 68
Address Detect ........................................ 153
Advance Information
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 228
H
Hardware Multiplier ............................................................ 79
I
I/O Ports ............................................................................ 81
ID Locations ............................................................. 183, 202
INCF ................................................................................ 228
INCFSZ ............................................................................ 229
In-Circuit Debugger .......................................................... 202
In-Circuit Serial Programming (ICSP) ...................... 183, 202
Independent PWM Mode
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ............................................. 254
Indirect Addressing ............................................................ 60
INFSNZ ............................................................................ 229
Initialization Conditions for all Registers ...................... 41–44
Instruction Cycle ................................................................ 49
Instruction Set .................................................................. 207
Table Reads and Table Writes .................................. 65
Write Sequence ......................................................... 71
Writing ....................................................................... 71
Introduction ................................................................ 79
Operation ................................................................... 79
Performance Comparison .......................................... 79
Duty Cycle Assignment ........................................... 131
Output ...................................................................... 131
Output, Channel Override ........................................ 132
and Standard PIC18 Instructions ............................. 254
Clocking Scheme ....................................................... 49
Flow/Pipelining .......................................................... 49
ADDLW .................................................................... 213
ADDWF ................................................................... 213
ADDWF (Indexed Literal Offset Mode) .................... 255
ADDWFC ................................................................. 214
ANDLW .................................................................... 214
ANDWF ................................................................... 215
BC ............................................................................ 215
BCF ......................................................................... 216
BN ............................................................................ 216
BNC ......................................................................... 217
BNN ......................................................................... 217
BNOV ...................................................................... 218
BNZ ......................................................................... 218
BOV ......................................................................... 221
BRA ......................................................................... 219
BSF .......................................................................... 219
BSF (Indexed Literal Offset Mode) .......................... 255
BTFSC ..................................................................... 220
BTFSS ..................................................................... 220
BTG ......................................................................... 221
BZ ............................................................................ 222
CALL ........................................................................ 222
CLRF ....................................................................... 223
CLRWDT ................................................................. 223
COMF ...................................................................... 224
CPFSEQ .................................................................. 224
CPFSGT .................................................................. 225
CPFSLT ................................................................... 225
Protection Against Spurious Writes ................... 73
Unexpected Termination ................................... 73
Write Verify ........................................................ 73
PIC18F1230/1330
DS39758C-page 301