PIC18F2331-E/MM Microchip Technology, PIC18F2331-E/MM Datasheet - Page 279

• Manufacturer Part Number: PIC18F2331-E/MM
• Description: IC MCU FLASH 4KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2331-E/MM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-QFN
• Core: PIC
• Processor Series: PIC18F
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 40 MHz
• Data Ram Size: 768 B
• Data Rom Size: 256 B
• On-chip Adc: Yes
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 5
• Height: 0.88 mm
• Interface Type: EUSART, I2C, SPI, SSP
• Length: 6 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V, 5.8 V
• Supply Voltage (min): 3.9 V, 4.2 V
• Width: 6 mm
• For Use With: I3-DB18F4431 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: PIC18F2331-E/ML; PIC18F2331-E/ML

23.5
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC
The user program memory is divided into five blocks.
One of these is a Boot Block of 512 bytes. The
remainder of the memory is divided into four blocks on
binary boundaries.
FIGURE 23-5:
TABLE 23-3:
 2010 Microchip Technology Inc.
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend:
Note 1:
®
devices.
File Name
Program Verification and
Code Protection
(PIC18F2331/4331)
Unimplemented
Unimplemented in PIC18F2331/4331 devices; maintain this bit set.
Shaded cells are unimplemented.
Boot Block
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
8 Kbytes
Read ‘0’s
Block 0
Block 1
SUMMARY OF CODE PROTECTION REGISTERS
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2331/2431/4331/4431
WRTD
Bit 7
CPD
—
—
—
—
0000h
0FFFh
0200h
0FFFh
1000h
1FFFh
3FFFh
Address
Range
EBTRB
WRTB
Bit 6
CPB
—
—
—
PIC18F2331/2431/4331/4431
MEMORY SIZE/DEVICE
(PIC18F2431/4431)
WRTC
16 Kbytes
Boot Block
Bit 5
Block 0
Block 1
Block 2
Block 3
—
—
—
—
—
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 23-5
for 8 and 16-Kbyte devices, and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in
Bit 4
—
—
—
—
—
—
0000h
01FFh
0200h
0FFFh
1000h
1FFFh
2000h
2FFFh
3000h
3FFFh
Address
Range
EBTR3
WRT3
CP3
Bit 3
shows the program memory organization
—
—
—
(1)
(1)
(1)
EBTR2
Block Code Protection
WRT2
CP2
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
Bit 2
—
—
—
Controlled By:
(1)
(1)
(1)
EBTR1
WRT1
Bit 1
CP1
DS39616D-page 279
—
—
—
Table
EBTR0
23-3.
WRT0
Bit 0
CP0
—
—
—