DSPIC33FJ12MC202-I/SP Microchip Technology, DSPIC33FJ12MC202-I/SP Datasheet - Page 16
![IC DSPIC MCU/DSP 12K 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ12MC202-I/SP
Manufacturer Part Number
DSPIC33FJ12MC202-I/SP
Description
IC DSPIC MCU/DSP 12K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ12MC201-ISO.pdf
(288 pages)
3.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
4.DSPIC33FJ12MC202-IML.pdf
(282 pages)
Specifications of DSPIC33FJ12MC202-I/SP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164337 - MODULE SOCKET FOR PM3 40DIPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- PIC24HJ12GP201-ISO PDF datasheet
- DSPIC33FJ12MC201-ISO PDF datasheet #2
- DSPIC33FJ12MC201-ISO PDF datasheet #3
- DSPIC33FJ12MC202-IML PDF datasheet #4
- Current page: 16 of 288
- Download datasheet (5Mb)
dsPIC33FJ12MC201/202
2.7
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < F
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV, and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration word.
2.8
If MPLAB ICD 2, MPLAB ICD 3, or MPLAB REAL ICE
in-circuit emulator is selected as a debugger, it
automatically initializes all of the A/D input pins (ANx)
as “digital” pins, by setting all bits in the AD1PCFGL
register.
The bits in the register that correspond to the A/D pins
that are initialized by MPLAB ICD 2, MPLAB ICD 3, or
MPLAB REAL ICE in-circuit emulator, must not be
cleared by the user application firmware; otherwise,
communication errors will result between the debugger
and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 2, MPLAB ICD 3, or MPLAB REAL
ICE in-circuit emulator is used as a programmer, the
user application firmware must correctly configure the
AD1PCFGL register. Automatic initialization of this
register is only done during debugger operation.
Failure to correctly configure the register(s) will result in
all A/D pins being recognized as analog input pins,
resulting in the port value being read as a logic ‘0’,
which may affect user application functionality.
DS70265D-page 14
Oscillator Value Conditions on
Device Start-up
Configuration of Analog and
Digital Pins During ICSP
Operations
IN
< 8 MHz to comply with device PLL
Preliminary
2.9
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternately, connect a 1k to 10k resistor to V
unused pins and drive the output to logic low.
Unused I/Os
© 2009 Microchip Technology Inc.
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