DSPIC33FJ12MC202-I/SP Microchip Technology, DSPIC33FJ12MC202-I/SP Datasheet - Page 60
![IC DSPIC MCU/DSP 12K 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ12MC202-I/SP
Manufacturer Part Number
DSPIC33FJ12MC202-I/SP
Description
IC DSPIC MCU/DSP 12K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.DSPIC33FJ12MC201-ISO.pdf
(288 pages)
3.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
4.DSPIC33FJ12MC202-IML.pdf
(282 pages)
Specifications of DSPIC33FJ12MC202-I/SP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Core Frequency
40MHz
Core Supply Voltage
2.75V
Embedded Interface Type
I2C, JTAG, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164337 - MODULE SOCKET FOR PM3 40DIPDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- PIC24HJ12GP201-ISO PDF datasheet
- DSPIC33FJ12MC201-ISO PDF datasheet #2
- DSPIC33FJ12MC201-ISO PDF datasheet #3
- DSPIC33FJ12MC202-IML PDF datasheet #4
- Current page: 60 of 288
- Download datasheet (5Mb)
dsPIC33FJ12MC201/202
EXAMPLE 5-2:
EXAMPLE 5-3:
DS70265D-page 58
; Set up NVMCON for row programming operations
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
; Perform the TBLWT instructions to write the latches
; 0th_program_word
; 1st_program_word
;
; 63rd_program_word
2nd_program_word
MOV
MOV
MOV
MOV
MOV
MOV
MOV
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
MOV
MOV
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
MOV
MOV
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
•
•
•
MOV
MOV
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
DISI
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x4001, W0
W0, NVMCON
#0x0000, W0
W0, TBLPAG
#0x6000, W0
#LOW_WORD_0, W2
#HIGH_BYTE_0, W3
#LOW_WORD_1, W2
#HIGH_BYTE_1, W3
#LOW_WORD_2, W2
#HIGH_BYTE_2, W3
#LOW_WORD_31, W2
#HIGH_BYTE_31, W3
#5
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
LOADING THE WRITE BUFFERS
INITIATING A PROGRAMMING SEQUENCE
Preliminary
;
; Initialize NVMCON
;
; Initialize PM Page Boundary SFR
; An example program memory address
;
;
; Write PM low word into program latch
; Write PM high byte into program latch
;
;
; Write PM low word into program latch
; Write PM high byte into program latch
;
;
; Write PM low word into program latch
; Write PM high byte into program latch
;
;
; Write PM low word into program latch
; Write PM high byte into program latch
; Block all interrupts with priority <7
; for next 5 instructions
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
; Insert two NOPs after the
; erase command is asserted
© 2009 Microchip Technology Inc.
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