AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 82
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AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
10.1.10
10.1.11
32099F–11/2010
PWMA
CAT
2. TWIM SMBAL polarity is wrong
1. BUSY bit is never cleared after writes to the Control Register (CR)
2. Incoming peripheral events are discarded during duty cycle register update
1. CAT asynchronous wake will be delayed by one AST peripheral event period
2. CAT QMatrix sense capacitors discharged prematurely
If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
The SMBAL signal in the TWIM is active high instead of active low.
Fix/Workaround
Use an external inverter to invert the signal going into the TWIM. When using both TWIM
and TWIS on the same pins, the SMBAL cannot be used.
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR when the PWMA is
disabled (CR.EN==0), the BUSY bit in the Status Register (SR.BUSY) will be set, but never
cleared.
Fix/Workaround
When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR, make sure the
PWMA is enabled, or simultaneously enable the PWMA by writing a one to CR.EN.
Incoming peripheral events to all applied channels will be discarded if a duty cycle update is
received from the user interface in the same PWMA clock period.
Fix/Workaround
Ensure that duty cycle writes from the user interface are not performed in a PWMA clock
period when an incoming peripheral event is expected.
If the CAT detects a condition that should asynchronously wake the chip in Static mode, the
asynchronous wake will not occur until the next AST event. For example, if the AST is gen-
erating peripheral events to the CAT every 50 milliseconds, and the CAT detects a touch at
t=9200 milliseconds, the asynchronous wake will occur at t=9250 milliseconds.
Fix/Workaround
None.
At the end of a QMatrix burst charging sequence that uses different burst count values for
different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the periph-
eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency.
This results in premature loss of charge from the sense capacitors and thus increased vari-
ability of the acquired count values. For example, if the PB clock frequency is 24MHz and
GCLK_CAT frequency is 6 MHz, n=4 and the Y lines may be incorrectly grounded for 0, 1, 2,
or 3 periods of the PB clock, depending on the relative phase of the PB and GCLK_CAT
clocks.
Fix/Workaround
Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11,
and/or 15) by writing ones to the corresponding odd bits of the CSARES register. For exam-
ple, if all 8 Y lines are implemented, write 0x0000AAAA to the CSARES register. When the Y
lines are incorrectly grounded by the CAT module for up to n-1 PB clocks at the end of burst
charging sequence, this will greatly reduce the amount of charge that is prematurely lost
from the sense capacitors, because the discharge time constant will now be approximately
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