AT32UC3L064-AUT Atmel, AT32UC3L064-AUT Datasheet - Page 94
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AT32UC3L064-AUT
Manufacturer Part Number
AT32UC3L064-AUT
Description
MCU AVR32 64KB FLASH 48TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.AT32UC3L-EK.pdf
(858 pages)
3.AT32UC3L016-D3HT.pdf
(110 pages)
Specifications of AT32UC3L064-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI/TWI/USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Package
48TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
50 MHz
Operating Supply Voltage
1.8|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3L064-AUT
Manufacturer:
HONGFA
Quantity:
30 000
Part Number:
AT32UC3L064-AUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
32099F–11/2010
8. Generic clock sources are kept running in sleep modes
9. DFLL clock is unstable with a fast reference clock
10. DFLLIF indicates coarse lock too early
11. DFLLIF dithering does not work
12. SCIF VERSION register reads 0x100
13. DFLLVERSION register reads 0x200
14. RCCRVERSION register reads 0x100
15. OSC32VERSION register reads 0x100
16. VREGVERSION register reads 0x100
If max step size is above 7, the DFLL might not lock at the correct frequency if the target fre-
quency is below 30MHz.
Fix/Workaround
If the target frequency is below 30MHz, use max step size (DFLL0MAXSTEP.MAXSTEP) of
7 or lower.
If a clock is used as a source for a generic clock when going to a sleep mode where clock
sources are stopped, the source of the generic clock will be kept running. Please refer to the
Power Manager chapter for details about sleep modes.
Fix/Workaround
Disable generic clocks before going to sleep modes where clock sources are stopped to
save power.
The DFLL clock can be unstable when a fast clock is used as reference clock in closed loop
mode.
Fix/Workaround
Use the 32KHz crystal oscillator clock or a clock with similar frequency as DFLLIF reference
clock.
The DFLLIF might indicate coarse lock too early, the DFLL will lose coarse lock and regain it
later.
Fix/Workaround
Use max step size (DFLL0MAXSTEP.MAXSTEP) of 4 or higher.
The DFLLIF dithering does not work.
Fix/Workaround
None.
The VERSION register reads 0x100 instead of 0x102.
Fix/Workaround
None.
The DFLLVERSION register reads 0x200 instead of 0x201.
Fix/Workaround
None.
The RCCRVERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
The OSC32VERSION register reads 0x100 instead of 0x101.
Fix/Workaround
None.
The VREGVERSION register reads 0x100 instead of 0x101.
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