AT89C5130A-RDRUM Atmel, AT89C5130A-RDRUM Datasheet - Page 143
AT89C5130A-RDRUM
Manufacturer Part Number
AT89C5130A-RDRUM
Description
MCU 8051 16K FLASH USB 64-VQFP
Manufacturer
Atmel
Series
AT89C513xr
Datasheet
1.AT89C5130A-PUTUM.pdf
(188 pages)
Specifications of AT89C5130A-RDRUM
Core Processor
C52X2
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
LED, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89STK-05
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
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4337K–USB–04/08
Table 21-8.
Note:
Reset Value = 80h when UEPNUM = 0 (default Control Endpoint)
Reset Value = 00h otherwise for all other endpoints
Bit Number
EPEN
1-0
7
7
6
5
4
3
2
1. (X = EPNUM set in UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number)
Bit Mnemonic Description
EPTYPE[1:0]
UEPCONX Register
UEPCONX (S:D4h)
USB Endpoint X Control Register
EPDIR
EPEN
DTGL
6
-
-
-
-
Endpoint Enable
Set this bit to enable the endpoint according to the device configuration. Endpoint 0 will
always be enabled after a hardware or USB bus reset and participate in the device
configuration.
Clear this bit to disable the endpoint according to the device configuration.
Reserved
The value read from this bit is always 0. Do not set this bit.
Reserved
The value read from this bit is always 0. Do not set this bit.
Reserved
The value read from this bit is always 0. Do not set this bit.
Data Toggle (Read-only)
This bit is set by hardware when a valid DATA0 packet is received and accepted.
This bit is cleared by hardware when a valid DATA1 packet is received and accepted.
Endpoint Direction
Set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints.
Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.
This bit has no effect for Control endpoints.
Endpoint Type
Set this field according to the endpoint configuration (Endpoint 0 will always be
configured as control):
00Control endpoint
01Isochronous endpoint
10Bulk endpoint
11Interrupt endpoint
5
-
4
-
DTGL
3
AT89C5130A/31A-M
EPDIR
2
EPTYPE1
1
EPTYPE0
0
143
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