AT89C5130A-RDRUM Atmel, AT89C5130A-RDRUM Datasheet - Page 97

• Manufacturer Part Number: AT89C5130A-RDRUM
• Description: MCU 8051 16K FLASH USB 64-VQFP
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5130A-RDRUM

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

Figure 19-4. Data Transmission Format (CPHA = 0)
Figure 19-5. Data Transmission Format (CPHA = 1)
Figure 19-6. CPHA/SS Timing
4337K–USB–04/08
MOSI (from Master)
SCK cycle number
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 0)
SCK (CPOL = 1)
MISO (from Slave)
SCK cycle number
SPEN (internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
Capture point
SPEN (internal)
SS (to Slave)
Capture point
SS (to Slave)
output data are shifted (Figure 19-4 and Figure 19-5). The clock phase and polarity should be
identical for the Master SPI device and the communicating Slave device.
As shown in
must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to
start the transmission. The SS pin must be toggled high and then low between each byte trans-
mitted (Figure 19-2).
Figure 19-6
ing its MOSI pin on the first SCK edge. Therefore the Slave uses the first SCK edge as a start
transmission signal. The SS pin can remain low between transmissions
mat may be preferable in systems having only one Master and only one Slave driving the MISO
data line.
MISO/MOSI
(CPHA = 0)
(CPHA = 1)
Master SS
Slave SS
Slave SS
shows an SPI transmission in which CPHA is’1’. In this case, the Master begins driv-
Figure
MSB
MSB
MSB
1
MSB
1
19-5, the first SCK edge is the MSB capture strobe. Therefore the Slave
2
bit6
bit6
2
bit6
Byte 1
bit6
3
bit5
bit5
3
bit5
bit5
bit4
4
bit4
bit4
4
bit4
Byte 2
bit3
bit3
5
bit3
bit3
5
6
bit2
bit2
6
bit2
bit2
Byte 3
7
bit1
bit1
7
bit1
AT89C5130A/31A-M
bit1
LSB
8
LSB
LSB
8
LSB
(Figure
19-1). This for-
97