AT89C5130A-RDRUM Atmel, AT89C5130A-RDRUM Datasheet - Page 159

• Manufacturer Part Number: AT89C5130A-RDRUM
• Description: MCU 8051 16K FLASH USB 64-VQFP
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5130A-RDRUM

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: AT89x
• Core: 8051
• Data Bus Width: 8 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89STK-05
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -

25.2
4337K–USB–04/08
WDT During Power-down and Idle
Table 25-2.
Reset value = XXXX X000
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-
down mode the user does not need to service the WDT. There are 2 methods of exiting Power-
down mode: by a hardware reset or via a level activated external interrupt which is enabled prior
to entering Power-down mode. When Power-down is exited with hardware reset, servicing the
WDT should occur as it normally should whenever the AT89C5130A/31A-M is reset. Exiting
Power-down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent
the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until
the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service
routine.
To ensure that the WDT does not overflow within a few states of exiting of power-down, it is bet-
ter to reset the WDT just before entering power-down.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT89C5130A/31A-M while in Idle mode, the user should always set up a timer that will periodi-
cally exit Idle, service the WDT, and re-enter Idle mode.
Number
Bit
7
6
5
4
3
2
1
0
7
-
Mnemonic
WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
Bit
S2
S1
S0
-
-
-
-
-
6
-
Description
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
WDT Time-out select bit 2
WDT Time-out select bit 1
WDT Time-out select bit 0
S2 S1 S0 Selected Time-out
0
0
0
0
1
1
1
1
16384x2^S machine cycles
0
0
1
1
0
0
1
1
5
-
0
1
0
1
0
1
0
1
16384x2^(214 - 1) machine cycles, 16.3 ms at FOSC = 12 MHz
16384x2^(215 - 1) machine cycles, 32.7 ms at FOSC = 12 MHz
16384x2^(216 - 1) machine cycles, 65.5 ms at FOSC = 12 MHz
16384x2^(217 - 1) machine cycles, 131 ms at FOSC = 12 MHz
16384x2^(218 - 1) machine cycles, 262 ms at FOSC = 12 MHz
16384x2^(219 - 1) machine cycles, 542 ms at FOSC = 12 MHz
16384x2^(220 - 1) machine cycles, 1.05 s at FOSC = 12 MHz
16384x2^(221 - 1) machine cycles, 2.09 s at FOSC = 12 MHz
4
-
3
-
AT89C5130A/31A-M
S2
2
S1
1
S0
0
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