DSPIC33FJ64GS606-E/MR Microchip Technology, DSPIC33FJ64GS606-E/MR Datasheet - Page 115
![MCU/DSP 16BIT 64KB FLASH 64QFN](/photos/12/13/121325/c04-149_mr_sml.jpg)
DSPIC33FJ64GS606-E/MR
Manufacturer Part Number
DSPIC33FJ64GS606-E/MR
Description
MCU/DSP 16BIT 64KB FLASH 64QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ32GS406-IPT.pdf
(418 pages)
Specifications of DSPIC33FJ64GS606-E/MR
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-VFQFN, Exposed Pad
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, QEI, POR, PWM, WDT
Number Of I /o
58
Ram Size
9K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Numeric And Arithmetic Format
Fixed-Point or Floating-Point
Instruction Set Architecture
Harvard
Device Million Instructions Per Second
40 MIPs
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
58
Data Ram Size
4 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
On-chip Dac
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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6.0
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: Software RESET Instruction
• WDTO: Watchdog Timer Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Condition Device Reset
FIGURE 6-1:
2010 Microchip Technology Inc.
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
RESETS
of the dsPIC33FJ32GS406/606/608/610
and
families of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Reset”
(DS70192) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able from the Microchip web site
(www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
MCLR
V
DD
dsPIC33FJ64GS406/606/608/610
Uninitialized W Register
RESET SYSTEM BLOCK DIAGRAM
Regulator
RESET Instruction
Internal
Sleep or Idle
Illegal Opcode
Module
WDT
Trap Conflict
V
DD
Detect
Glitch Filter
Rise
Preliminary
BOR
POR
A simplified block diagram of the Reset module is
shown in Figure 6-1.
Any active source of reset will make the SYSRST
signal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state and some are unaffected.
All types of device Reset sets a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 6-1).
A POR clears all the bits, except for the POR bit
(RCON<0>), that are set. The user application can set
or clear any bit at any time during code execution. The
RCON bits only serve as status bits. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
Note:
Refer to the specific peripheral section or
Section 3.0 “CPU” of this data sheet for
register Reset states.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
SYSRST
DS70591C-page 115
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