DSPIC33FJ64GS606-E/MR Microchip Technology, DSPIC33FJ64GS606-E/MR Datasheet - Page 53
![MCU/DSP 16BIT 64KB FLASH 64QFN](/photos/12/13/121325/c04-149_mr_sml.jpg)
DSPIC33FJ64GS606-E/MR
Manufacturer Part Number
DSPIC33FJ64GS606-E/MR
Description
MCU/DSP 16BIT 64KB FLASH 64QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet
1.DSPIC33FJ32GS406-IPT.pdf
(418 pages)
Specifications of DSPIC33FJ64GS606-E/MR
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-VFQFN, Exposed Pad
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, QEI, POR, PWM, WDT
Number Of I /o
58
Ram Size
9K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Numeric And Arithmetic Format
Fixed-Point or Floating-Point
Instruction Set Architecture
Harvard
Device Million Instructions Per Second
40 MIPs
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
58
Data Ram Size
4 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Interface Type
I2C, SPI, UART
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
On-chip Dac
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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4.2.5
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
The X data space is used by all instructions and
supports all addressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to pro-
vide two concurrent data read paths.
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, though the
implemented memory locations vary by device.
2010 Microchip Technology Inc.
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
X AND Y DATA SPACES
Preliminary
4.2.6
Some devices contain 1 Kbyte of dual ported DMA
RAM, which is located at the end of Y data space.
Memory locations that are part of Y data RAM and are in
the DMA RAM space are accessible simultaneously by
the CPU and the DMA controller module. DMA RAM is
utilized by the DMA controller to store data to be
transferred to various peripherals using DMA, as well as
data transferred from various peripherals using DMA.
The DMA RAM can be accessed by the DMA controller
without having to steal cycles from the CPU.
When the CPU and the DMA controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.
DMA RAM
DS70591C-page 53
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