PIC24FJ256GA108-E/PT Microchip Technology, PIC24FJ256GA108-E/PT Datasheet - Page 198
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PIC24FJ256GA108-E/PT
Manufacturer Part Number
PIC24FJ256GA108-E/PT
Description
IC PIC MCU FLASH 256KB 80-TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ128GA008-IPT.pdf
(12 pages)
2.PIC24FJ128GA106-IPT.pdf
(14 pages)
3.PIC24FJ128GA106-IPT.pdf
(330 pages)
4.PIC24FJ128GA106-IPT.pdf
(52 pages)
5.PIC24FJ128GA110-EPT.pdf
(310 pages)
Specifications of PIC24FJ256GA108-E/PT
Program Memory Type
FLASH
Program Memory Size
256KB (85.5K x 24)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
68
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA240015 - BOARD MCV PIM FOR 24F256GADM240011 - KIT STARTER MPLAB FOR PIC24F MCU
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ256GA108-E/PT
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
PIC24FJ256GA108-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC24FJ128GA008-IPT PDF datasheet
- PIC24FJ128GA106-IPT PDF datasheet #2
- PIC24FJ128GA106-IPT PDF datasheet #3
- PIC24FJ128GA106-IPT PDF datasheet #4
- PIC24FJ128GA110-EPT PDF datasheet #5
- Current page: 198 of 330
- Download datasheet (3Mb)
PIC24FJ256GA110 FAMILY
REGISTER 17-2:
DS39905E-page 198
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15,13
bit 14
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-6
Note 1:
URXISEL1
UTXISEL1
R/W-0
R/W-0
2:
Value of bit only affects the transmit properties of the module when the IrDA
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See
Section 10.4 “Peripheral Pin Select”
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
UTXINV: IrDA
IREN = 0:
1 = UxTX Idle ‘0’
0 = UxTX Idle ‘1’
IREN = 1:
1 = UxTX Idle ‘1’
0 = UxTX Idle ‘0’
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
0 = Sync Break transmission disabled or completed
UTXEN: Transmit Enable bit
1 = Transmit enabled; UxTX pin controlled by UARTx
0 = Transmit disabled; any pending transmission is aborted and the buffer is reset, UxTX pin controlled
UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full; at least one more character can be written
TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
URXISEL<1:0>: Receive Interrupt Mode Selection bits
11 = Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer.
URXISEL0
UTXINV
R/W-0
R/W-0
cleared by hardware upon completion
by port
the transmit buffer becomes empty
operations are completed
least one character open in the transmit buffer)
Receive buffer has one or more characters.
UxSTA: UARTx STATUS AND CONTROL REGISTER
(1)
®
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
Encoder Transmit Polarity Inversion bit
UTXISEL0
ADDEN
R/W-0
R/W-0
(2)
RIDLE
U-0
R-1
—
for more information.
HC = Hardware Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0 HC
UTXBRK
PERR
R-0
(1)
UTXEN
R/W-0
FERR
R-0
(2)
®
encoder is enabled (IREN = 1).
2010 Microchip Technology Inc.
x = Bit is unknown
UTXBF
OERR
R/C-0
R-0
URXDA
TRMT
R-1
R-0
bit 8
bit 0
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