PIC18F4525-E/ML Microchip Technology, PIC18F4525-E/ML Datasheet - Page 189
![IC MCU FLASH 24KX16 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F4525-E/ML
Manufacturer Part Number
PIC18F4525-E/ML
Description
IC MCU FLASH 24KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2525-ISO.pdf
(412 pages)
3.PIC18F2525-ISO.pdf
(18 pages)
4.PIC18F2525-ISO.pdf
(18 pages)
5.PIC18F2525-ISO.pdf
(6 pages)
6.PIC18F2525-ISO.pdf
(6 pages)
Specifications of PIC18F4525-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3986 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
1 x 8
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, 53275-917, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13 bit
For Use With
I3DB18F4620 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC18F2221-ISO PDF datasheet
- PIC18F2525-ISO PDF datasheet #2
- PIC18F2525-ISO PDF datasheet #3
- PIC18F2525-ISO PDF datasheet #4
- PIC18F2525-ISO PDF datasheet #5
- PIC18F2525-ISO PDF datasheet #6
- Current page: 189 of 412
- Download datasheet (7Mb)
17.4.7
In I
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
Q2 and Q4 clocks. In I
reloaded automatically.
FIGURE 17-17:
TABLE 17-3:
© 2008 Microchip Technology Inc.
Note 1:
2
C Master mode, the Baud Rate Generator (BRG)
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
4 MHz
Fosc
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
BAUD RATE
2
C interface does not conform to the 400 kHz I
I
2
C™ CLOCK RATE W/BRG
SSPM3:SSPM0
BAUD RATE GENERATOR BLOCK DIAGRAM
2
C Master mode, the BRG is
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
1 MHz
SCL
F
CY
SSPM3:SSPM0
CY
PIC18F2525/2620/4525/4620
) on the
Reload
Control
CLKO
20 MHz
20 MHz
20 MHz
F
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
2 MHz
CY
* 2
Reload
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
2
BRG Down Counter
C specification (which applies to rates greater than
SSPADD<6:0>
BRG Value
1Fh
0Ch
18h
63h
09h
27h
02h
09h
00h
F
OSC
/4
(2 Rollovers of BRG)
DS39626E-page 187
400 kHz
400 kHz
333 kHz
312.5 kHz
1 MHz
100 kHz
308 kHz
100 kHz
100 kHz
F
SCL
(1)
(1)
(1)
(1)
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