PIC18F4525-E/ML Microchip Technology, PIC18F4525-E/ML Datasheet - Page 22
![IC MCU FLASH 24KX16 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F4525-E/ML
Manufacturer Part Number
PIC18F4525-E/ML
Description
IC MCU FLASH 24KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2525-ISO.pdf
(412 pages)
3.PIC18F2525-ISO.pdf
(18 pages)
4.PIC18F2525-ISO.pdf
(18 pages)
5.PIC18F2525-ISO.pdf
(6 pages)
6.PIC18F2525-ISO.pdf
(6 pages)
Specifications of PIC18F4525-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-QFN
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3986 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
1 x 8
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, 53275-917, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13 bit
For Use With
I3DB18F4620 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC18F2221-ISO PDF datasheet
- PIC18F2525-ISO PDF datasheet #2
- PIC18F2525-ISO PDF datasheet #3
- PIC18F2525-ISO PDF datasheet #4
- PIC18F2525-ISO PDF datasheet #5
- PIC18F2525-ISO PDF datasheet #6
- Current page: 22 of 412
- Download datasheet (7Mb)
PIC18F2525/2620/4525/4620
TABLE 1-3:
DS39626E-page 20
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
Legend: TTL = TTL compatible input
Note 1:
RD0
PSP0
RD1
PSP1
RD2
PSP2
RD3
PSP3
RD4
PSP4
RD5
PSP5
P1B
RD6
PSP6
P1C
RD7
PSP7
P1D
2:
3:
Pin Name
ST = Schmitt Trigger input with CMOS levels
O
Default assignment for CCP2 when the CCP2MX Configuration bit is set.
Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.
For the QFN package, it is recommended that the bottom pad be connected to V
= Output
PIC18F4525/4620 PINOUT I/O DESCRIPTIONS (CONTINUED)
PDIP
19
20
21
22
27
28
29
30
Pin Number
QFN TQFP
38
39
40
41
2
3
4
5
38
39
40
41
2
3
4
5
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
Buffer
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
CMOS = CMOS compatible input or output
I
P
PORTD is a bidirectional I/O port or a Parallel Slave
Port (PSP) for interfacing to a microprocessor port.
These pins have TTL input buffers when the PSP
module is enabled.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
Digital I/O.
Parallel Slave Port data.
Enhanced CCP1 output.
= Input
= Power
Description
© 2008 Microchip Technology Inc.
SS
.
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