ATMEGA168-15AZ Atmel, ATMEGA168-15AZ Datasheet - Page 14
![MCU AVR 16K FLASH 15MHZ 32-TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA168-15AZ
Manufacturer Part Number
ATMEGA168-15AZ
Description
MCU AVR 16K FLASH 15MHZ 32-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA168-15AZ.pdf
(340 pages)
Specifications of ATMEGA168-15AZ
Package / Case
32-TQFP, 32-VQFP
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
23
Eeprom Size
512 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
1K x 8
Program Memory Size
16KB (16K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
I²C, SPI, UART/USART
Core Size
8-Bit
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Interface Type
2-Wire/USART/Serial
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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4.8.1
5. AVR ATmega48/88/168 Memories
5.1
14
In-System Reprogrammable Flash Program Memory
ATmega48/88/168 Automotive
Interrupt Response Time
When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in this example.
The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-
mum. After four clock cycles the program vector address for the actual interrupt handling routine
is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.
The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If
an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed
before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt
execution response time is increased by four clock cycles. This increase comes in addition to the
start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and the I-bit in SREG is set.
This section describes the different memories in the ATmega48/88/168. The AVR architecture
has two main memory spaces, the Data Memory and the Program Memory space. In addition,
the ATmega48/88/168 features an EEPROM Memory for data storage. All three memory spaces
are linear and regular.
The ATmega48/88/168 contains 4/8/16K bytes On-chip In-System Reprogrammable Flash
memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is orga-
nized as 2/4/8K x 16. For software security, the Flash Program memory space is divided into two
sections, Boot Loader Section and Application Program Section in ATmega88 and ATmega168.
ATmega48 does not have separate Boot Loader and Application Program sections, and the
SPM instruction can be executed from the entire Flash. See SELFPRGEN description in section
“Store Program Memory Control and Status Register – SPMCSR” on page 258
more details.
The Flash memory has an endurance of at least 75,000 write/erase cycles. The
ATmega48/88/168 Program Counter (PC) is 11/12/13 bits wide, thus addressing the 2/4/8K pro-
gram memory locations. The operation of Boot Program section and associated Boot Lock bits
for software protection are described in detail in
page 256
ATmega168” on page
on Flash Programming in SPI- or Parallel Programming mode.
Assembly Code Example
C Code Example
sei
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
and
; set Global Interrupt Enable
“Boot Loader Support – Read-While-Write Self-Programming, ATmega88 and
263.
“Memory Programming” on page 278
“Self-Programming the Flash, ATmega48” on
contains a detailed description
and
7530I–AVR–02/10
page
268for
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